搜索资源列表
CPLD
- 在文件夹YL2440_CPLD中有做好的CPLD工程,请用Xilinx ISE 6.2打开.
timer
- 用C语言实现在Xlinx公司的FPGA的延时程序在ISE软件编程环境下-With the C language implementation in the Xlinx the company' s FPGA-delay procedures in ISE software programming environments
how-to-make-a-testbench
- 怎样写一个testbench 讲述了怎样在ise或者modelsim里面怎样写仿真测试-How to write a testbench about how how to write a simulation test in ise modelsim inside
xilinx-ise-13.1-operation-flow
- 此文档介绍了如何在xilinx ise 13.3的开发环境里面进行开发，并将程序下载到xilinx fpga里面-This document describes how to development, and download the program to the inside of xilinx fpga xilinx ise 13.3 development environment inside
CPU
- 在THINPAD平台上的50M时钟5级流水支持THCOMIPS指令集的CPU，并附带8核扩展，内有详细实验报告。全部用VHDL编写，并附有样例验证程序，开发环境为ISE 14.1。-Water support THCOMIPS instruction set CPU 50M clock the THINPAD platform 5 and comes with an 8-core extension, within a detailed test report. All written usin
I2C
- fpga实现i2C通信程序,工程文件可以直接用ISE打开-FPGA implementation of i2C communication program
PipelineCPU
- 1. understand how to improve CPU performance 2. master the working principle of pipelined MIPS microprocessor. 3. understand the concept of data adventure, control risk and the solution of pipeline conflict. 4. mastering the testing method of pipe