搜索资源列表
signal_cpu_sort
- Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_ME
verilog
- 8bit alu use verilog hdl
ALU
- 用verilog编写的4位ALU,由算术运算模块、逻辑运算模块、选择模块组成
CPU
- 用Verilog实现的 哈佛结构的简单指令集CPU程序,由ALU、地址译码器、指令译码器等部分组成-Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.