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embedded_risc
- 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
AUDIO_DAC
- 一个关于声音处理的Verilog语言编写的解码芯片，可以用于FPGA处理芯片的IP核，欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
8088verilog
- intel 8088 架构的verilog代码，可以综合下载，在fpga上实现8088调试。-intel 8088 verilog structure of the code can be integrated download, fpga achieved in 8088 debugging.
arm7_core_verilog
- arm7timi架构的verilog代码，可以仿真，通过学习，可以掌握arm7内部架构。-arm7timi verilog structure of the code can be simulated, through learning, be able arm7 internal structure.
risc8
- PIC单片机的verilog实现，不记得在哪里下载的。源文件中应该有的。-PIC MCU Verilog realized, can not remember where to download. Source file should have.
Mips_Top
- 是verilog做的简化mips32指令系统。 有些小问题，用就能发现，是学习的好资料。 如果有必要，可以和我联系。-Verilog do is simplify the MIPS32 instruction set. Some small problems, and use can be found, is to learn from good information. If necessary, can contact me.
sdModel
- SD Card的verilog模拟模型，可以配合开发SD Controller使用-SD Card the verilog simulation model can be used with the development of SD Controller
24xx02-Verilog-Model
- 24xx02 Verilog Model 在官网上下载的 eepROM 可以参考-Download on the official website 24xx02 Verilog Model eepROM can refer to
PipelineCPU
- 这是我们设计的一个MIPS流水线CPU，基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于，5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型，这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句，从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU
source
- 快速傅里叶变换verilog程序,其中包含了多个模块，全部在芯片了就可以实现，不用查找表-Fast Fourier Transform verilog program, which contains a number of modules, all in a chip can be achieved without a lookup table
lcd_stop_watch
- verilog在1602上顯示時間，並可以調時間，整點報時-verilog display the time in 1602, and can adjust the time, the whole point timekeeping
verilog-CAN-protocol-realization
- CAN协议的verilog实现，欢迎大家下载-verilog CAN protocol realization, welcome to download