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Verilog_example
- 本文件包括多路选择器器建模，译码器实验程序，加法器实验程序，比较器实验程序，计数器建模，I2C接口标准建模源码，串行接口RS232标准建模源码标准，LCM建模源码，时钟６分频源码，串并转化源码。 ，对于硬件设计初学者来说有一定的参考价值。
Serialadder
- VHDL语言串行加法器 可以实现五位加法运算-Serial adder five addition operations can be achieved
8bitadder
- 串行8位加法器工程，已编译成功.标准代码VHDL语言-Serial 8-bit adder works have been compiled successfully
pipeline
- 用流水线构成的串行八位加法器，可以输出进位级联-With a line consisting of eight serial adder, can output binary cascade
adder_4
- 三种设计模式的加法器，分别是行为及描述，串行模式，并行模式。希望对大家了解加法器有帮助-Adder three design models, and behavior were described, the serial mode, the parallel mode. I hope to help everyone understand adder
vhdl
- 通过VHDL语言，实现简单的多路选择器、串行加法器、并行加法器、计数器-By VHDL language, a simple multiple-choice, serial adder, parallel adder, counter
adder
- 四位二进制串行加法器 VHDL语言 EPM240 数字逻辑实验-Four serial binary adder VHDL language EPM240 digital logic test
shiyan_1
- 这是一个使用VHDL编写的串行加法器程序，简单易用，是初学者必备-This is a serial prepared using VHDL adder program, easy to use, is essential for beginners
code
- A、B两串行数据转换为并行数据，然后进入加法器模块，进行相加输出。-A, B two serial data is converted to parallel data, and then enter the adder module, add the output.
Serial_Adder
- 注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加-Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder