搜索资源列表
VHDL学习的好资料--18个VHDL实验源代码
- 20个VHDL实验源代码,包括: 1 交通灯控制器 2 格雷码变换器 3 BCD码加法器 4 四位全加器 5 四人抢答器 6 4位并行乘法器 9 步长可变加减计数器 10 可控脉冲发生器 11 正负脉宽数控信源 12 序列检测器 13 4位流水乘法器 14 出租车计费器 15 多功能数字钟 16 多功能数字秒表 17 频率计 18 七人表决器 19 数码锁 20 VGA彩条发生器
vga.rar
- 最全的FPGA VGA方面的资料及源码. VGA IPcore的Verilog代码 VGA接口设计实例及测试程序 VGA接口设计实例及测试程序(源码) VGA显示源码,FPGA VGA most comprehensive information and source code. VGA IPcore the Verilog code VGA interface design and testing procedures VGA interface design and testing p
RX
- 1路视频光端机的接收端,VHDL源码,使用全FPGA芯片的硬件,内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
TX
- 1路视频光端机的发射端,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
123654vhaing
- 八音自动播放电子琴设计 vhdl源码,文件内有具体注释 [VHDL-XILINX-EXAMPLE26.rar] - [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9- -Octave electronic keyboard play aut
2fsk_final
- 全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code
seven
- 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器,通过独特的3次映射一位全加器的方法从而实现七人表决器的功能,与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full a
add
- 一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
F7-2VT-1DR
- 2路视频光端机的,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-2-way video PDH' s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
Adder4
- 源码,内容是用VHDL语言编写的四位全加器-Source code, using VHDL language of the four full-adder
data_interleaver_ise10migration
- ofdm通信系统交织的Verilog实现,源码中有两个错误,第二处少了一个begin 第一处为全角半角,自己写一下就行-ofdm data_interleaver
counter_four
- 模拟了半加器和全加器的vhdl语言源码。-model half add and full add mechine vhdl code
source
- verilog HDL程序设计教程,随书附赠的源码包,涵盖很多常用模块,内容很全。-verilog HDL programming tutorials, source code packages bundled with the book, covering many commonly used modules are very informative.
8051core-Verilog
- MCU 8051源码经过FPGA验证,功能全-mcu 8051 code
verilog
- verilog应用非常全的例子,里面包含了几乎所有的应用例子,是您学习FPGA的非常好的源码-verilog example of application is very wide, which contains almost all of the application examples, you learn a very good source of FPGA
BCD_add
- BCD全加器,用QuartuesII 开发的源码,包括工程文件,下载就能用的,在DE2-70上直接使用。-BCD full adder, with QuartuesII source development, including the project file, download will be able to use in directly on the DE2-70.
huanxingfenpeiqi
- 步进电机的环形分配器,VHDL文件源码,经编译全通过,没有仿真,-Annular distributor of the stepper motor, VHDL file source, compile the whole through, there is no simulation.
FPGA-VGA
- 最全的FPGA-VGA方面的资料及源码,对于初学者来说非常有帮助 -failed to translate
VHDL-8-wei-quan-jia-qi
- 原理图输入法实现8位全加器,内含vhd源码文件和一份word介绍文件,管脚配置已经完成,芯片为EPIK30TCI443-Schematic entry method 8-bit full adder, and a source code file containing the vhd file word descr iption, pin configuration has been completed, the chip is EPIK30TCI443
Verilog_prj
- 特权同学BJ-EPM240 CPLD开发板配套视频源码文件,ex1~ex15全,是入门Verilog的首选。-Privileged students BJ-EPM240 CPLD development board supporting the video source files, ex1 ~ ex15 whole, is the first choice of entry Verilog.