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Max_Plus_II-_tutorial
- Max+plusII(或写成Maxplus2,或MP2) 是Altera公司推出的的第三代PLD开发系统(Altera第四代PLD开发系统被称为：QuartusII，主要用于设计新器件和大规模CPLD/FPGA).使用MAX+PLUSII的设计者不需精通器件内部的复杂结构。设计者可以用自己熟悉的设计工具（如原理图输入或硬件描述语言）建立设计，MAX+PLUSII把这些设计转自动换成最终所需的格式。其设计速度非常快。Maxplus2被公认为是最易使用，人机界面最友善的PLD开发软件，特别适合初学者
danpianjixitongban
- 全国大学生电子设计竞赛单片机最小系统版-内含原理图、系统版等文档和图。-National Undergraduate Electronic Design Contest SCM minimum system version- includes schematics, system version and other documents and plans.
xlx_s3a_evl-sch
- Xilinx SP3 开发板电路原理图，是学FPGA设计和电路设计的参考资料。-Xilinx SP3 development board circuit diagram, is to learn FPGA design and circuit design reference.
FPGA_SCH
- 联华众科FA161电原理图 联华众科FA161电原理图 联华众科FA161电原理图-UMC congregation Division FA161 Circuit Diagram
EXCD1yuanlitu
- EXCD-1 Spartan 3E开发板原理图-EXCD-1 Spartan 3E development board schematics
Jshuqi
- 基于VHDL原理图实现的计数器 时钟晶振为48MHZ -Schematic-based VHDL implementation of the counter clock oscillator is 48MHZ
UART11
- uart实现，原理图方式，介绍串口实现的模块及实现方式-uart implementation schematic way to introduce the serial interface modules and implementations
ADV7441A-Evaluation-Board-Documents
- ADI 744x HDMI输入，输出原理图，包括电源，接口，以及FPGA等原理图-ADI 744x HDMI input, output, schematics, including power supplies, interface, and other schematic FPGA
Quartus
- 本设计是实现基于FPGA的液晶显示模块，采用自顶向下的设计方法，用原理图的形式实现顶层控制。-The design is FPGA-based liquid crystal display module, using top-down design method, to achieve top-level schematic in the form of control.
EP2C_sch
- Cyclone2开发板原理图。学习Altera必备利器。-Cyclone2 development board schematics. Altera essential learning tool.
H2C35-V6-core
- FPGA开发板原理图，核心板的，EP2C系列的，希望对大家有帮助-FPGA development board schematics, core board, EP2C series, we want to help
ALTERA_USB
- altera usb制作资料 包括原理图软件及硬件程序语言-altera cpld usb Blaster
f_subber
- 用Quartus开发的全减器设计，用原理图实现的。-By using Quartus development of the whole design, implemented using schematics.
full_add
- 全加器，基于原理图设计的全加器。经过时序仿真验证-Full adder, based on the schematic design of the full adder. After timing simulation
biaojueqi
- 四路表决器。原理图设计。经过时序仿真验证。-Four voting machine. Schematic design. After a timing simulation.
sy6
- 数字钟的VHDL源程序，里面附有数字钟的VHDL源程序和原理图的数字钟电路，数字钟有en,clk,clr等接口。-Digital clock in the VHDL source code, which the VHDL source code with a digital clock and schematic of the digital clock circuit digital clock with en, clk, clr and other interfaces.
PLD-LOGIC_SPWM
- 电子设计竞赛中获二等奖，在FPGA中实现的两路自然采样SPWM，原理图输入法设计，1024*八位正弦查找表，带FSK和ASK调制功能，频率范围8KHz~12KHz.-Electronic Design Competition second prize in the FPGA to achieve the two natural sampling SPWM, schematic design input, 1024* eight sine look-up table, with FSK and A
SG_FPGA
- 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the devic
LittleM
- 小ｍ序列的生成；VHDL语言；使用原理图设计法-Small m sequence generation VHDL language use of schematic design
1
- Cyclone III FPGA Starter Kit的原理图，orcad格式-Cyclone III FPGA Starter Kit schematic, orcad format