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Verilog_code_for_AWGN.rar
- verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。,verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence.
awgn
- 高斯白噪声的VHDL实现。伪随机序列只能输出均匀噪声，需要打乱相关性。-awgn in vhdl
M12
- VHDL硬件描述语言实现M12序列，可以用作白噪声，码率可调-VHDL hardware descr iption language M12 sequence can be used as white noise, adjustable rate
gwnseq
- verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）-verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence
m
- 这是vhdl编写的产生7位m序列的程序，类比可以产生更多为的。而m序列即可作为输入测试信号，也可以模拟噪声。-It is written vhdl 7 m sequence generation process, can produce more for the analogy. The m-sequence can be used as an input test signal, it can simulate noise.
m0_array_Serial_to_parallel
- 采用m序列产生随机序列，然后通过对其进行串转并的转换输出8位，连接AD0832可以观察到噪声。-The m sequence is used to generate random sequence, and then through the serial to turn and the output of 8 bits, the connection of ad0832 can be observed in noise.