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VLSI-Project-Median-filer
- FPGA和ASIC实现的图像中值滤波模块,各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the
FPGA-based-image-median-filtering
- 基于FPGA的图像中值滤波,在xilinx的FPGA上实现了算法,采用matlab的算法最终通过了验证。-FPGA-based image median filtering on xilinx FPGA implementation of the algorithm, using matlab algorithm finally passed validation.