搜索资源列表
EDA
- 数字钟的实现 FPGA上运行 VHDL编写-Digital clock running on the FPGA to achieve the preparation of VHDL
shuzizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟,并具有定时与闹钟功能,能在设定的时间发出闹铃音,能非常方便地对小时、分钟和秒进行手动调节以校准时间,每逢整点,产生报时音报时。 实验平台: 1. 一台PC机; 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, d
shuzizhong
- 可预置数字钟,用VHDL语言编写,LED显示,普通数字钟表。-Digital clock can be preset using VHDL language, LED display, an ordinary digital watch.
shuzizhong2008
- 本文描述了数字钟的设计方案和具体的设计步骤及代码,功能比较全面,可以直接用作课程设计!-This paper describes the design of digital clock program and the specific design steps and code, function more comprehensive and can be directly used for curriculum design!
clock
- 数字钟设计,有分秒显示,上下午显示,可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
clock
- 用高速硬件语言VHDL设计的全功能数字钟,经测试运行稳定-VHDL language used high-speed hardware design full-function digital clock, tested and stable operation
ssz
- 数字钟,用VHDL写的各个模块,顶层用图形编辑,在实验箱上完全通过-Digital clock, using VHDL written by various modules, top-level graphics editing, in the experimental box completely through
EDA
- 基于VHDL语言,用Top_Down的思想进行设计的数字钟。-Based on the VHDL language, using design thinking Top_Down the digital clock.
clock
- 软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
clock
- 用VHDL实现的完整数字钟代码,时分秒计时、校时、整点仿电台报时。-Used to achieve a complete VHDL code digital clock, accurate time at school, the whole point of imitation time radio.
shuzizhong
- 基于vhdl的数字钟完整工程文件,已在实验箱上实现-vhdl clock
clk
- Quartus II工程压缩文件,是一个典型的基于FPGA的数字钟工程项目,有50MHz分频、计数、译码等模块。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules.
SHUZIZHONGVHDL
- 多功能数字钟的VHDL编程实现,有与其他数字钟不同的秒表,闹钟等更多功能-Multi-function digital clock of VHDL programming, digital clock with other different stopwatch, alarm clock function, such as more
clock_digital
- 用Verlog HDL编写的数字钟程序,包含时,分,秒,进位,解码,扫描显示等功能。-Written by Verlog HDL ,a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.
shuzizhong
- 这时用VHDL语言编写的多功能数字钟,具有正常的计时功能,还能进行校时、校分,并且具有整点报时功能-Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of
VHDL_for_clock
- 基于VHDL语言的数字钟设计,附有完整的程序代码,并有仿真结果。-VHDL-based digital clock design, with a complete code, and have the simulation results.
DZZ1
- 多功能数字钟 能进行正常的时、分、秒计时功能, 分别由6个数码管显示24小时、60分钟、60秒钟的计数器显示。 2. 能利用实验系统上的按键实现“校时”“校分”功能: 3. 能利用扬声器做整点报时-VHDL
e7v4
- 数字钟:显示,设置时间,设置闹铃(报时),秒表。 平台:quartusII 5.1。 说明:此版本中已将系统时钟调快,自己稍微改动一下即可,小小的考验,做出来会更有成就感!-digital clock:display time, set time, set alarm(use speaker to alarm), stopwatch. platform: quartusII 5.1 comment: there s a place to change if you want th
SZZ
- 这是一个数字钟的VHDL语言,具有调时、调秒、调分功能,同时,还具有十二小时制向二十四小时制切换功能-This is a digital clock in VHDL language, with a tune, the tone seconds and sub-transfer function, while the system also has 12 hours to 24 hours the system switching function
vhd_design
- 我学习VHDL的课程设计,是多功能数字钟,有闹钟,秒表等功能,多指教-I learned VHDL course design is multi-functional digital clock, there is an alarm clock, stopwatch functions, multi-Zhi Jiao