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second&clk
- 开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路
pcm_verilog
- 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
存储器模型及测试台
- 512x8存储器模型,及其测试台，用verilog写-512x8 memory model, and the tester, using Verilog write
FourBitsCounter
- 四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型-quaternary counter module, the use of VHDL language, in which ISE8.1 tested model
Cpu_model
- Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
bfm
- Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
firmatlab
- fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
fftmatlab
- fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
ddsmatlab
- dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
sinmdlmatlab
- 正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
VerilogHDLchinapub
- Verilog HDL硬件描述语言 01简介.PDF 02HDL指南.PDF 03语言要素.PDF 04表达式.PDF 05门电平模型化.PDF 06用户定义原语.PDF 07数据流模型化.PDF 08行为建模.PDF 09结构建模.PDF 10其它论题.PDF 11验证.PDF 12建模实例.PDF 13语法参考.PDF-Verilog HDL Hardware Descr iption Language Introduction 01. P
baseonVerilog
- 基本运算逻辑和它们的Verilog HDL模型-basic arithmetic logic and their Verilog HDL model
NAND01GR3B_VH1
- nand flash NAND01GR3B (st)的仿真模型 （VHDL） 的-nand flash NAND01GR3B (st), the simulation model (VHDL)
adc8888
- 8位的a/d行为模型，可以应用于modelsim等环境下的仿真，不可综合。-eight of the a / d behavior model can be applied to other environments modelsim the simulation, not comprehensive.
sram__
- 静态随机读取存储器行为模型，可以应用于modelsim环境的仿真。-static random acts of reading memory model can be applied to the simulation environment modelsim.
VERILOGCOMP
- 设计一个字节（8 位）比较器。 要求：比较两个字节的大小，如a[7:0]大于 b[7:0]输出高电平,否则输出低电平,改写测试 模型,使其能进行比较全面的测试 。 -design a byte (8) for comparison. Requirements : To compare the size of two bytes, as a greater than [7:0] b [7:0] output margin. Otherwise, low-level output, re
MT29FxxG08xx.rar
- MT的NAND FLASH MT29FxxG08xx系列的Verilog仿真模型，包含详细说明，试验证明，非常准确。,MT of the NAND FLASH MT29FxxG08xx series of Verilog simulation model, contains a detailed descr iption, testing proved very accurate.
sdram 仿真模型
- sdram 仿真模型,用于verilog代码sdram行为级仿真-sdram modelsim model
ModelCPU
- 包含模型机设计的框架代码 可手动添加其他相关代码完成各种功能设计(The framework code that contains model machine design can be added manually)