搜索资源列表
M-150_tm_eng
- M-150II打印机芯开发资料,广泛用于出租车记价器与消防记录仪!
m.rar
- 扩频接收机设计的部分，一个用vhdl语言编写的m序列生成器，,A language with vhdl generator sequence m
fpdpsk
- FSK/PSK信号调制器的VHDL程序，共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode
Matlab-m-sequence-generator
- 介绍m序列和教你如何利用matlab进行编译m序列-Introduction of m-sequences and teach you how to use the matlab compiled m-sequence
M-sequence-generator
- M sequence generator using VHDL-M sequence generator
M
- 小M序列发生器。序列长度为7。方便修改。-Small M sequence generator. Sequence length is 7. Facilitate the change.
m
- 由20位移位寄存器线性反馈产生的m序列的vhdl代码-20-bit shift register linear feedback sequence generated vhdl code m
m
- m序列生成文件，带有我自己写的仿真，结果在modelsim6.0f中生成正确。-m sequence generation file, written with my own simulation results generated in the modelsim6.0f correct.
LIP1732CORE_system_mbus_arbiter
- System Verilog M bus arbiter module
m_sequencer
- m序列发生器，长度可以变化，此处使用长度为40 的移位寄存器。反馈函数使用的是：x40+x5+x4+x3+1-m sequence generator, the length can be varied. here the length of the shift register is 40. Feedback function : x40+ x5+ x4+ x3+1
m
- m序列产生器，verilog语言实现,在FPGA上试验过-m code maker
Verilog----m
- verilog 编写的m 序列，可以直接使用。-verilog written m-sequence can be used directly.
FPGA-M-sequence-generator
- FPGA VHDL 语言M序列发生器，可以帮助各位需要的朋友探讨研究-FPGA VHDL language M-sequence generator, can you help a friend in need of research
m-xulie
- 频率可步进M序列发生器 从10K 到100K ,步进为10K VERILOG编写-M-sequence generator frequency step from 10K to 100K, the preparation step for the 10K VERILOG
i2cEeprom
- A simulation model for the 24Cxx series of I2C EEPROMs from M. Neumann (Hamburg univ) used for verification of a I2C-master
M-sequence
- M序列具有伪随机特性，代码包含了M序列的生成和检测，可用于帧同步系统。-M-sequence has a pseudo-random properties, including the M-sequence code generation and detection, can be used for frame synchronization system.
m-operand-n-bit-adder
- n bit m operand adder
N-bits-by-M-bits
- 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier
M-series-digital-signal
- 第一路用于产生一个10Mbps的M序列，第二路产生10Kbps到100Kbps的M序列，数据率可以按10Kbps步进。-The first way to generate a sequence of M 10Mbps, the second way to produce 10Kbps to 100Kbps M-sequence data rate can 10Kbps steps.
m
- 这是vhdl编写的产生7位m序列的程序，类比可以产生更多为的。而m序列即可作为输入测试信号，也可以模拟噪声。-It is written vhdl 7 m sequence generation process, can produce more for the analogy. The m-sequence can be used as an input test signal, it can simulate noise.