搜索资源列表
yyy
- 能检测11100101的序列，时钟信号控制输入的序列。-11,100,101 sequence can detect the clock signal control input sequences.
4v2
- ENTITY maj IS PORT(a,b,c : IN BIT m : OUT BIT) END maj --Dataflow style architecture --Behavioural style architecture using a look-up table ARCHITECTURE using_table OF maj IS BEGIN PROCESS(a,b,c) CONSTANT lookuptable : BIT_VEC
FPGAs-101
- very good book about fpga likeeee
3ASendReceive_SameData101110_Console
- Sparten-3A收发_间隔产生相同分组101-110_控制程序，用于发送数据包。-Sparten-3A interval produced the same group receive _ 101-110_ control program, used to send packets.
s101
- 用VHDL语言，设计一个“101”序列检测器，双过程描述编写-VHDL language, to design a dual procedure describes the preparation of "101" sequence detector.
HW2
- It s about find string 101 and 110 in bit stream
VHDL-32bit-add
- 功能实现：“1015+1016+1017+...+1115” 101个数的累加（1s/次） 数码管显示结果，结果为1015、2031、3048、40-The functions: " 1015+1016+1017+ the ...+1115" 101 the number of cumulative (1s/time) digital tube display results, results 1015,2031,3048,4066 ...
seq_detector
- 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test so
shujujiance
- 单进程Mealy型数据监测。实现100101的数据监测，可实现多次组合监测，更改移植方便简单。-Mealy-type single-process data monitoring. Achieve 100,101 data monitoring, enabling multiple portfolio monitoring, change transplantation convenient and simple.
VHDL 101 Everything you need to Know
- VHDL 101 Everything you need to Know.rar