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双路脉冲发生器（veralog）
- Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is wr
dpram_fpga
- 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
sdram_control
- 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
assignmentP2
- 1. Access the relevant reference books or technical data books and give accurate definitions for the following timing parameters: (1) propagation time tPD, (2) transition time tTD, (3) setup time tSU, (4) hold time tHD, and (5) clock-to
Counter
- 用Verilog语言实现的74*163计数器，Quratus II编译通过-Verilog language with 74* 163 counters, Quratus II compiled by
ECC_4_29
- 优化的163位ECC 公钥生产（点乘）模块，40us-ECC public key 163 optimized production (the dot) module, 40us
Counter
- 用VERILOG语言实现的74*163 计数器，代码十分简单易懂，适合数字逻辑电路实验的初学者-With the VERILOG language implementation of the 74* 163 counter, the code is very simple and easy to understand, suitable for digital logic circuit experiment for beginners
LCD12864
- 该程序用于CPLD控制12864显示,显示内容见http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8734321251-The program is used to control CPLD 12864，link:http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8734321251 to view
lcd1602
- 该程序通过CPLD控制1602显示，显示效果见http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8732102150-CPLD to control the program by 1602, the display see http://zhuxiangqing.blog.163.com/album/# m = 2 & aid = 264724219 & pid = 8732102150