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  1. DCT_vhdl

    1下载:
  2. IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100% synthesizable-IDCT-M is a medium speed
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:10.48kb
    • 提供者:陈朋
  1. 1DCT_VHDL

    0下载:
  2. VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:10.53kb
    • 提供者:NULL
  1. dct

    0下载:
  2. all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2016-06-14
    • 文件大小:1kb
    • 提供者:haziq36
  1. VLSI-Architectures-for-Discrete-Wavelet-Transform

    0下载:
  2. VLSI architecture and VHDL codes for 1D and 2D DWT and IDWT schemes.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:951.83kb
    • 提供者:Sameet A. Khan
  1. shift_arr

    0下载:
  2. This contains the shift array which can be used in 2D DCT with help of 2 1D DCTs.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-27
    • 文件大小:1.79kb
    • 提供者:Prashanth
  1. uvm-1.1d.tar

    1下载:
  2. UVM World 官方发布的UVM(通用验证方法学)的源代码,基于SystemVerilog,用于ASIC Verification。2013-03最新发布版本uvm-1.1d.tar.gz-The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-09
    • 文件大小:3.07mb
    • 提供者:吴杉
  1. FILTER

    0下载:
  2. VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION -VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.3kb
    • 提供者:gsp
  1. 8-bit-RISC_CPU

    0下载:
  2. 8位RISC_CPU设计的verilog源码以及工程文件、测试数据文件。在modelsim 10.1d下验证成功,打开工程文件即可使用。-8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-26
    • 文件大小:185.57kb
    • 提供者:
  1. uvm-1.1

    1下载:
  2. 学习IC验证的好资料,包括UVM-1.1a和UVM-1.1d的全部工程example,适合IC验证基于UVM平台的初学者。-Learn good about IC verification, including all engineering of UVM-1.1a and UVM-1.1d, for beginners based on the UVM platform for IC verification.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-12-12
    • 文件大小:6.89mb
    • 提供者:李菲
  1. modelsim_10.1d破解工具

    0下载:
  2. modelsim_10.1d破解工具 modelsim_10.1d破解工具(modelsim_10.1d crack tools)
  3. 所属分类:VHDL/FPGA/Verilog

  1. crc7

    0下载:
  2. 以crc7为例进行UVM的验证 Part 1: 搭建环境。 本文使用的Quartus II 13.1(64 bit),器件库MAX V。写了一个Verilog的简单的crc7。 仿真环境是ModelSim 10.2c。虽说自带UVM库。但是,没找到Modelsim自带的uvm_dpi.dll,于是,还重新编译了一番。 本文在win 10下。下载uvm-1.1d(现在最新版本有1.2d了),放好。(crc7 code by system verilog language)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-04-22
    • 文件大小:8.64mb
    • 提供者:viviergan
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