搜索资源列表
mc8051-VHDL
- VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core
8-cpu
- 8位CPU的VHDL设计,16条指令系统,以及部分测试代码,开发工具是quartusii_60_pc
MICO8_DEMO_03_18_08.ZIP
- Lattice 超精简8位软核CPU--Mico8，开放所有源代码，包括VHDL，编译器，支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。,Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to supp
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
CPU
- 用VHDL编的简易16位和8位CPU，可完成加减乘法移位等功能，拥有源码和设计文档，资料齐全-Compiled with VHDL simple 16-bit and 8-bit CPU, to be completed by addition and subtraction multiplication shift functions, with source code and design documents, data and complete
CPU
- 八位简单risc cpu 设计的源代码，VHDL语言写的-8 Simple risc cpu design source code, VHDL language written
freerisc8_11
- 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
RISC
- hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
computer6
- 8位CPU软核设计与应用研究-8-bit CPU design and application of soft-core research .......
_8bitcpu
- 8 bit cpu vhdl design code not tested
risc
- 用Verilog 编写的8位risc cpu，行为级描述，可综合-6 bits risc cpu by Verilog
Simple8bitCPU
- VHDL Source Code for Simple 8-bit CPU
cpu16
- Verilog下描述16位CPU，虽然有点简单，但具有一定的可读性，内附夏宇闻老师的8位CPU文档-Verilog descr iption of 16-bit CPU, though a bit simple, but with a certain degree of readability, XIA Yu-Wen teachers containing 8-bit CPU Documentation
cpu25
- 8 bit cpu code using vhdl it performs various operations
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
plan
- using the VHDL, 8bit cpu plan
CPU
- Cpu with 8 bits in VHDL verilog Code
cpu
- 8位CISC模型计算机设计，包括加减法存储输出的运算-8-bit CISC model of computer design, including the addition and subtraction operations stored output
cpu
- 设计一个简化的处理器（字长8位），并使其与内存MEM连接，协调工作。用VHDL以RTL风格描述。该处理器当前执行的指令存放在指令寄存器IR中。处理器的指令仅算逻指令和访问内存指令）。-Design a simplified processor (8-bit word length), and connect it with the memory MEM, and coordination. Described with VHDL in RTL style. The processor is c
cpu
- 实现一个简单的8位cpu，具有基本的运算指令和控制指令，可扩展-Implement a simple 8-bit cpu, have a basic command and control operations instruction, scalable