his design is a comparator that compares consecutive bits a0...a3 with b0...b3

ARM7 Verilog 代码及设计文档,代码及设计-ARM7 Verilog code and design documents, code and design

4位并行加法器，a3,a2,a1,a0,b3,b2,b1,b0,cin为输入，cout,s3,s2,s1,s0为输出-4-bit parallel adder, a3, a2, a1, a0, b3, b2, b1, b0, cin as the input, cout, s3, s2, s1, s0 as the output