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双路脉冲发生器（veralog）
- Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is wr
fifo_01
- 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8 -- 8-bit Identity Comparator -- uses 1993 std VHDL --
decode_for_m68008
- -- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X\"00000\" to X\"01FFF\" -- csbar(1) : X\"40000\" to X\"43FFF\" -- csbar(2) : X\"08000\" to X\"0AFFF\" -- csbar(3) : X\"E000
mo0re_FSM
- -- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn--- Moore State Machine with explicit state encoding -- dowload from : www.fpga.com.cn
FSM02
- 异步复位状态机 -- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn -asynchronous reset state machine -- State Machine with Asynchronou 's Reset -- dowload from : www.fpga.com.cn
BoothMultiplier
- -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthe
wave_gen
- 波形发生器，带TESTBENCH， 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH.
dpram_fpga
- 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
sdram_control
- 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
ISE8.1_loopback
- 硬件平台为Xilinx Spartan3e，编译软件为ISE8.1，实现了九针com口通信，键盘输入回显，switch控制LED功能。-hardware platform for Xilinx Spartan3e, compile software ISE8.1. achieved nine needles com port communication, a return to the keyboard input, LED control switch function.
EP1C3_12_9_DDS
- 直接数字式频率合成器(DDS)设计实验(电子设计竞赛赛题) 其它详细资料说明请参考 http://www.kx-soc.com-direct digital frequency synthesis (DDS) experimental design (Electronic Design Contest tournament title) said other details Please refer to prescribed http://www.kx-soc.com
RS232_Interrupt_Code_niosII
- 串口中断＿niosII.rar 解压密码：www.21control.com
jtag
- verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
BiDirectionalCell
- verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
ControlCell
- verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
InputCell
- verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证
QuartusIIhelp2
- Program: eSupport.com BIOS Agent Version 3.66 BIOS Date: 10/31/08 BIOS Type: American Megatrends BIOS ID: 64-0100-000001-00101111-103108-Cantiga-N80VC207 OEM Sign-On: BIOS Date: 10/31/08 Ver: 207-Program: eSupport.com BIOS Agent Version 3.6
COM-AND-VGAsheji
- 讲述FPGA对COM串口的控制，及VGA传输的操作，值得学习借鉴-About FPGA control of COM ports, and VGA transfer operation, it is worth learning from
LCD-Driver-And-Keyboard-char-Asm(www.bargh20.com)
- LCD Driver And Keyboard char Asm(www.bargh20.com)
num_clock-www.21ic.com
- 可以在FPGA板上实现数钟的整点报时，闹钟等功能-num_clock 21ic.com