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ARM9_instruction_cache_verilogCodes
- Arm9指令Cache缓存模块的verilog代码，对一些做ARM硬件开发的朋友有参考价值。-Arm9 Instruction Cache Cache Module Verilog code, do some of the hardware development of the ARM friends reference value.
jop_core_cache
- JOP的内核缓存源码，不易找到，大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits
deinterlace
- Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序，比普通算法效果有很大改进。-Xilinx to provide a linear interpolation for the cache interlaced progressive change procedures, than ordinary algorithm results are greatly improved.
cache
- 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
cameralink
- 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示 系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示
ping_pong_buffer
- 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
cache
- 缓存器 cache verilog 欢迎下载偶-cache verilog
pingpang
- 关于乒乓操作的，对于数据缓存有很大的用处-On the ping-pong operation of data cache for the great usefulness of
dCACHE
- Vhdl写的数据cache,根据Verilog程序改编-Vhdl write data cache
iCACHE
- 用VHDL写的数据cache，基于Verilog版本改编过来-To use VHDL to write the data cache, based on the Verilog version of the adaptation over
CIC_Moore
- It is a complete project of Cache Interface Controller programmed in VHDL using the logic of Moore State Machine
cache
- 本文给出了一个cache的所有源代码，存为txt格式的压缩包-this is a code of a cache
CPUwithout-cache
- 5级流水无cache,CPU实验，是学习VHDL的好资料，对于了解CPU很有帮助！-5-stage pipeline without cache, CPU test, is learning VHDL good information, very helpful for understanding the CPU!
code-water-no-cache
- 5级流水无cache的cpu代码，基于verilog，串行，两级流水-cpu code with no water nor cache
run time expandable cache
- Expandable cache proposed by Bournoutian and Orailoglu is very efficient in reducing miss rate and energy consumption with small area overhead. However, the original expandable cache with only one expansion scheme may lead to thrashing problems. In t
cache
- 利用VHDL语言，仿真cache与主存的关系，使用了类似数组的方法。-using vhdl,tell us the relation between cache and memory.
cache
- 使用Verilog实现对cache命中判断的模拟-Use Verilog to realize the simulation of the cache hit judgment
cache
- verilog 语言写的一个cache 平台是xillix ISE 实现了从cache中取指令命中和缺失情况的处理 -Verilog language to write a cache Platform is ISE xillix The processing of the instruction hit and the missing the cache is realized.
D_cache
- 数据缓存的模块设计，连接流水线mem模块。(The module of data cache is designed to connect the pipeline MEM module.)