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quaddecoder_verilog_ise11.2_used_09042010
- Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y
e1framerdeframer
- E1 Framer/De-Framer, Also include the data check (CRC) and channel coding/decoding-E1 framer and deframer, clock adjust, clock phase adjust
LDPC
- 讲述了LDPC信道编解码的基本原理及各种算法，是一篇很好的综述性的文章 -Describes the LDPC channel coding and decoding of the basic principles and various algorithms, is a good review of the article
scr_20
- 完成20位并行数据的伪随机序列扰码，配合解码部分，提高数字信道的SNR。已经通过综合仿真，并正在具体项目中运行，未发现任何缺点。-Completion of the 20 data-parallel pseudo-random sequence scrambling code with the decoding part, improve the SNR of the digital channel. Through integrated simulation, and run specific
descr_20
- 完成20位并行数据的伪随机序列解码，配合扰码部分，提高数字信道的SNR。已经通过综合仿真，并正在具体项目中运行，未发现任何缺点。-Completion of the 20 pseudo-random sequence of parallel data decoding, with part of the scrambling code, and to improve the SNR of the digital channel. Through integrated simulation, an
SRC_2CH
- 2通道HDCVI视频光端机：实现两个高速AD转换采集HDCVI信号，编码扰码后通过光纤远距离传输，对端收到后解码通过高速DA转换为HDCVI信号。-2 channel HDCVI video Guangduan Ji: two high-speed AD acquisition signal conversion HDCVI, scrambling code via the optical fiber remote transmission, receives an end after deco
verilog-juanjima
- 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and