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costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
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- 基于matlab和QuartusII开发的无线通信FPGA设计,内有(matlab代码,Verilog代码,缩略语表.doc)注释详细,代码数十个,总有一个是你喜欢的!-Matlab and QuartusII based on the development of wireless communications FPGA design, there are (matlab code, Verilog code abbreviations. Doc) Notes detail dozens of
costas_loop
- 集中式插入式帧同步发的verilog源代码-concentrative inserted frame sync
costas
- 载波同步，costas环，基于Verilog的载波同步环-Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
cotas
- Costas环是用来解调双边带抑制载波信号的,也是二相或四相移相键控信号解调的专用环路-Costas loop is used to double sideband suppressed carrier signal demodulation, and also two-phase or four phase shift keying signal demodulation of the special loop
CostasLoop
- costas loop in vhdl -costas loop in vhdl ...
Costas
- 介绍了某直接序列扩频、QPSK调制系统接收通道中四相Costas 载波跟踪环的原理及其基于 DSP+FPGA 的实现-Introduced a direct-sequence spread spectrum, QPSK modulation system, receive path Costas carrier tracking loop four-phase principle and its implementation based on DSP+ FPGA
costasc_verilog
- 实现costas环，用verilog语言实现，缺少乘法器，可以自己添加-Realization of Costas ring, with the Verilog language implementation, the lack of multiplier, you can add their own.
COSTAS_LOOP
- 使用ISE12.1编写的Costas环，用于载波恢复，直接使用了IP核中的FIR和DDS模块-Use ISE12.1 written Costas loop for carrier recovery, the direct use of the IP core of FIR and DDS module
costas_DPSK
- 采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps，载波频率12KHz，采样率1.6MHz， 输入数据位宽12位，快捕带为799.617Hz-Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 79
costas
- costas锁相环matlab仿真代码，对costas环的研究和硬件实现具有指导意义。-Costas Phase-Loop MATLAB Code.
costas
- matlab科斯塔斯环的仿真，有波形，很实用的程序(matlab costas m programm)