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VerilogHDLchinapub
- Verilog HDL硬件描述语言 01简介.PDF 02HDL指南.PDF 03语言要素.PDF 04表达式.PDF 05门电平模型化.PDF 06用户定义原语.PDF 07数据流模型化.PDF 08行为建模.PDF 09结构建模.PDF 10其它论题.PDF 11验证.PDF 12建模实例.PDF 13语法参考.PDF-Verilog HDL Hardware Descr iption Language Introduction 01. P
verilog_intr
- Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports – Data Types – Assigning Values and Numbers – Operators – Behavioral Modeling • Continuous Assignments • Procedural Blocks –
std_logic_1164
- 这个包定义了vhdl标准,为设计者在使用数据类型时建立用于vhdl的互连模型。-This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.
Example-4-16
- 串并转换建模 数据流串并转换的实现方法多种多样，根据数据的排序和数量的要求，可以选用移位寄存器、RAM等来实现。对于数据量比较小的设计来说，可以使用移位寄存器完成串并转换；对于排列顺序有规定的串并转换，可以用case语句判断实现；对于复杂的串并转换，还可以用状态机实现-Modeling serial data stream and convert the realization of string and convert many ways, sort and quantity of the
verilog-Streamline-tutorial
- Verilog HDL 语言具有下述描述能力：设计的行为特性、设计的数据流特性、设计的结构 组成以及包含响应监控和设计验证方面的时延和波形产生机制。所有这些都使用同一种建模 语言。此外， Verilog HDL语言提供了编程语言接口，通过该接口可以在模拟、验证期间从设 计外部访问设计，包括模拟的具体控制和运行。-Has the following descr iption of Verilog HDL language ability: the behavior of the des
Interactive-state-machine
- 交互状态机建模，交互状态机能够使用通过公共寄存器通信的独立的a l w a y s语句进行描述。 示的两个交互进程的状态图， T X是一个发送器， M P是一个微处理器。如果进程T X不忙，进 程M P将要发送的数据放置在数据总线上，然后向进程T X发送信号L o a d T X，通知其装载数据 并开始发送数据。进程T X在数据传送期间设置T X B u s y表明其处于忙状态，不能从进程M P接 收任何进一步的数据。-Interactive state machine mode
Experiment10
- FPGA低级建模试验二串口定时发送数据，通过板级调-FPGA test two low-level modeling time to send serial data transfer through the board
fifo_module
- 基于vhdl的FIFO建模，主要是用于输入输出数据缓存-Vhdl-based FIFO modeling is mainly used for input and output data cache
divid
- 基于VHDL的divided建模，方便调用，主要是除法运算，用于数据移位-Divided modeling based on VHDL, call the main division operation is used to shift data
muti
- 基于VHDL的乘法器算法建模，主要用于数据移位-Multiplier algorithm based on VHDL modeling, used mainly for data shift
VHDL-Code-For-Half-Adder-By-Data-Flow-Modeling.zi
- VHDL Code For Half Adder By Data Flow Modeling
dataflow
- 4:2 encoder using data flow modeling
and_data
- this program is done in verilog hdl and it is program of AND gate DATA level modeling program-this program is done in verilog hdl and it is program of AND gate DATA level modeling program
nand_data
- this program is done in verilog hdl and it is program of AND gate DATA level modeling program-this program is done in verilog hdl and it is program of AND gate DATA level modeling program
DSP
- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001 VHDL Data-Flow modeling KEYWORD: generate, array, range, constant and subtype- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001
7054
- Iterative self-organizing data analysis, Relief computing classification weight, NRZ type differential phase modulation signal modeling and simulation analysis.