搜索资源列表
OpenSPARC_DDR2_controller_RTL_
- 基于FPGA的DDR2控制程序，用verilog编写的。,FPGA-based DDR2 control procedures, prepared by using Verilog.
Micron_SDRAM_DDR2Simulation_mo
- DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme,DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
DDR2 SDRAM 控制器的FPGA实现
- DDR2 SDRAM 控制器的FPGA实现,DDR2 SDRAM controller FPGA to achieve
DDR2_16bit
- ddr2原理图设计，原厂电路图设计，很好很强大 16bit-ddr2 schematic design, the original schematic design, a very powerful 16bit
DDR2_Memory_Test
- DDR2 controller which contains verilog files，pdf and so on
Crack_QII81_FULL_License
- quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
Spartan6_DDR2-
- Spartan6 硬核MCB读写DDR2 实战篇-Spartan6 real hard-core DDR2 MCB articles to read and write
ddr_ddr2_sdram9.0
- altera 公司提供的ddr_ddr2_sdram9.0，DDR2 SDRAM 源代码-altera provided ddr_ddr2_sdram9.0, DDR2 SDRAM source code
DDR2_ctrl
- DDR2 SDRAM控制器的设计及FPGA验证
c4gx_f896_host_ddr2a_odt
- ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码-ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code
DDR2Controller
- DDR2 Controller DDR2 Controller
ddr2sdram_spartan3s700an.tar
- It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Sparta
modelsim_ddr2sdram_spartan3s700an.tar
- Modelsim DDR2 SDRAM files
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
ddr2
- 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
s3ask_ddr2
- DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
The-Speedy-DDR2-Controller-
- The Speedy DDR2 Controller For FPGAs ERSA 2009 Final
~DDR2-Demonstration
- 基于Xilinx-FPGA的DDR2演示代码-DDR2 Reference design which Based on Xilinx-FPGA
ddr2
- ddr2的功能控制模块，3部分，只要调取就可以。-ddr2 control codes