搜索资源列表
VHD
- RS编码中用到的交织和去交织程序,VHDL描述,交织深度8-nterlace with VHDL,depth is 8
VHDL-quick-start
- descr iption of VHDL Quick introduction to VHDL – basic language concepts – basic design methodology • Use The Student’s Guide to VHDL or The Designer’s Guide to VHDL – self-learning for more depth – reference for project work-desc
Xilinx
- 深入详解xilinx fpga结构,是初学者学习xilinx fpga的好工具-Detailed xilinx fpga-depth structure for beginners to learn is a good tool for xilinx fpga
Channel_EstimationMIMO
- 本文对MIMO技术中的信道估计、空时编码和单载波频域均衡技术(SC-FDE)及其在FPGA上的实现进行了深入的研究-In this paper, MIMO channel estimation techniques, space-time coding and single-carrier frequency domain equalization (SC-FDE) and its implementation on FPGA-depth study carried out
fifo
- 高性能设计中常用的fifo模型,采用单端读取数据的方式,数据的位宽以及fifo的深度可以设置。通过modelsim仿真-Fifo design commonly used in high-performance models, using single-ended way to read data, the data bit width and the depth of the fifo can be set. Modelsim simulation by
viterbi
- 硬判决viterbi译码的硬件实现,通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Verilog_HDL
- verilog语言的全面教程,从基础到深入,可以让初学者快速正握verilog语言的编程。-verilog language, comprehensive tutorials, from basic to in-depth, beginners can quickly grasp verilog language is the programming.
altera_SignalTap_II
- SignalTap II 嵌入逻辑分析仪集成到 Quartus II 设计软件中,能够捕获和 显示可编程单芯片系统(SOPC)设计中实时信号的状态,这样开发者就可以在整 个设计过程中以系统级的速度观察硬件和软件的交互作用。它支持多达 1024 个 通道,采样深度高达 128Kb,每个分析仪均有 10 级触发输入/输出,从而增加了 采样的精度。SignalTap II 为设计者提供了业界领先的 SOPC 设计的实时可视性, 能够大大减少验证过程中所花费的时间。-SignalTa
awsdasdsa
- VHDL应用高级技巧 适合深入学习VHDL-VHDL-depth study and application of advanced techniques for VHDL
CPLD--fpga
- VHDL高级应用技巧 设和深入学习VHDL者-Senior VHDL application skills and in-depth study and VHDL are based
fpga-jingyan
- 关于fpga的开发经验之谈,大家可以通过这个更加深入的了解fpga-About the development of the fpga experience,Everybody can get through this more in-depth
sin
- 函数信号发生器,采样深度64,最佳工作频率1K--100KHz-Function generator, sampling depth 64, the best frequency 1K- 100KHz
beijingdaxue_verilog_pdf
- 北大的verilogHDL教程,从潜入深,逐步深入的讲解,但是许多重点都被提到了,是不错的教程。-Peking University verilogHDL tutorial from dive deep, and gradually in-depth explanations, but many have been referred to the focus, is a good tutorial.
Verilog
- 针对Verilog语言,提供了135个经典的示例程序代码,从简单到复杂,一步步的深入。-For the Verilog language, providing 135 classic example code, from simple to complex, step by step in depth.
fifo
- 详细介绍了fifo深度计算的方法,fifo深度的计算是面试中常被问到的问题!-Fifo depth details of the method of calculation, fifo depth calculation is frequently asked interview questions!
FIFO
- verilog 实现FIFO存储功能,八位数据宽度,16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
Verilog_integer_reg
- 深入探讨verilog中integer与reg两者的区别,从综合与实现的角度介绍-Depth in the integer and reg verilog difference between the two, from the point of introduction and implementation of comprehensive
LectureNote
- 高级Xilinx FPGA ISE设计教程,详细讲解优化Xilinx设计结构改善时序,减少implementation时间,减少调试时间,片上验证以及调试等FPGA设计深入环节,是深入理解FPGA设计的不可多得的好书。-Advanced Xilinx FPGA ISE design tutorial, explain in detail the structure of the Xilinx design optimization to improve timing, reduce implem
FIFO-verilog
- 本实验完成的是8位异步FIFO的设计,其中写时钟100MHz,读时钟为5MHz,其中RAM的深度为256。当写时钟脉冲上升沿到来时,判断写信号是有效,则写一个八位数据到RAM中;当读时钟脉冲上升沿到来时,判断读信号是有效,则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志,不能再往RAM再写数据;当RAM中数据读空时产生一个空标志,不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design,
4Verilog-FIFO
- FIFO的简单编程,该FIFO的深度为4,宽度为32,其接口类型见文件中的图标及其注释。-This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example,