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generic_fifos
- 用HDL语言编写的通用fifo源码，通过对fifo的宽度和深度进行配置，可以产生我们所需要的fifo，还包括fifo的测试程序和仿真Makefile脚本-with HDL prepared by the General fifo source, fifo of the breadth and depth configuration, can produce what we need fifo. also included fifo testing procedures and simulatio
Synthesizable_FIFO_verilog
- Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is
CAN--for-FPGA
- FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错-FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA
CAN--for-FPGA FPGA控制SJA1000实现CAN协议
- FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错-FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
fifoi
- 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
ch5ex
- 几个稍微深入的时序逻辑电路和状态机的VHDL代码-Several little-depth sequential logic circuit and state machine of the VHDL code
FPGA
- FPGA工程师作为目前比较热门的职业，相对薪酬比较高，要求FPGA有一定深度的理解和应用的能力，面试的题目也比较难，这些是一些公司题目的汇总-FPGA Engineer, as the current hot jobs, the relative pay is relatively high, the requirements FPGA must have the depth of understanding and application of the ability to interview
VHDL_USERGUIDE
- 本书的主要的服务对象是熟悉硬件系统，而对软件的设计经验缺乏的工程师；叙述了VHDL的用法-This guide is intended for the engineer who is familiar with the principles of hardware design, but has little experience in designing with a language-based synthesis system. It describes the general c
fifo
- 用VHDL语言写的FIFO代码，可设FIFO的深度-VHDL language with code written in FIFO, FIFO depth can be set up
RAM
- 曾经做过一电子竞赛课题部分，硬件描述语言VHDL做数据存储器512位存储深度，-Competition has been a subject of electronic parts, hardware descr iption language VHDL do data memory storage depth of 512,
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
VHDLquickstart
- Quick introduction to VHDL – basic language concepts – basic design methodology • Use The Student’s Guide to VHDL or The Designer’s Guide to VHDL – self-learning for more depth – reference for project work-Quick introduction to VHDL
kzhdverilogyf
- 国内关于verilog hdl书讲解比较浅，没深度，对于读者应该查看verilog hdl英文标准-Nations on the book to explain verilog hdl more shallow, lacking depth, for English readers should see the standard verilog hdl
SystemVerilogEventRegionsRaceAvoidanceGuidelines.r
- The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This pap
CONVOLUTIONAL_INTERLEAVER
- DVB数据交织,交织深度I=12,已得到应用!-DVB data interleaving, interleaving depth I = 12, has been applied!
verilog
- This book provides a comprehensive introduction to the modern study of computer algorithms. It presents many algorithms and covers them in cons iderable depth, yet makes their design and analysis access ible to all levels of readers. We have trie
lcd12864
- 采用FPGA实现12864液晶的显示，较1602复杂，但原理基本相同，深入学习FPGA-12864 FPGA implementation using liquid crystal display, compared with 1602 complex, but basically the same principle, in-depth learning FPGA
elecfans.com-VHDL
- vhdl深入学习教程，包括数据对象以及实例等，本书详细介绍了数据对象类型以及应用方法等-vhdl-depth tutorials, including data objects and example, the book details the data object types and application methods
ISE-10.1-In-Depth-Tutorial
- 针对ISE10.1快速入门手册的近一步深化的说明手册，对更多更深入的功能进行了介绍和示例-Quick Start Manual for ISE10.1 taking a step forward to deepen the instruction manual for more in-depth features for more descr iption and examples were