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entropy_coding
- 用verilog 描述的嫡编码(entropy coding) 应用于图像压缩编码 有测试文档 -using Verilog His descr iption of coding (entropy coding) for image compression test files are encoded
ongame
- 一个游戏 the hardware for the game includes a number of displays, each with a button and -- a light, that each represent a bin that can store marbles (beans). -- -- The display indicates the number of marbles in each bin at any given time. --
PhaseNoise.rar
- 小数分频技术解决了锁相环频率合成器中的频率分辨率和转换时间的矛盾, 但是却引入了严重的相位噪声, 传统的相位补偿方法由于对Aö D 等数字器件的要求很高并具有滞后性实现难度较大。$2 调制器对噪声具有整形的功 能, 因而将多阶的$2 调制器用于小数分频合成器中可以很好地解决他的相位噪声的问题, 大大促进了小数分频技术的 发展和应用。文章最后给出了在GHz 量级上实现的这种新型小数分频合成器的应用电路, 并测得良好的相噪性能。,Fractional-N technology to s
prat5
- This code allows an application with the state machine in VHDL and his conception
DE2_demonstrations
- DE2开发板上的资料,主要是他的例子,含有各种接口程序,如VGA,USB,LCD等-DE2 development board information, mainly his example, contain a variety of interface program, such as VGA, USB, LCD, etc.
top
- 交织的vhdl实现，希望对大家有帮助，同他学习！-VHDL-cutting to achieve, I hope all of you help with his learning!
SN7485
- his design is a comparator that compares consecutive bits a0...a3 with b0...b3
alu_code_asif
- vhdl code for ALU.i think by reading his code..it will be very easy for you to design an Alu.
Digitalclocksignal
- 数字时钟信号用vhdl语言描述的源代码他光放利用到各个电路中-Vhdl digital clock signal with the source code language to describe his use of light to release all circuits
adder16b
- 潘松那本书上用vhdl语言描述的16位并入并处加法器-Pan book vhdl language used to describe the 16-bit adder into his
dianfengshan
- 能实现智能风扇控制,包括模式选择.摇头.定时等功能.-To achieve the smart fan control, including the mode selection. Shook his head. Timing functions.
ourdev_247126
- his design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The
qiangdaqi
- 四人抢答器，已通过编译，仿真，包括抢答识别、计分、计时、数字显示等功能。-Four Responder, has passed the compilation, simulation, including the answer in his identification, scoring, timing and digital display.
quartus_project
- verilog的一些代码，都是自己写的，欢迎拍砖-verilog some of the code is written in his welcome Paizhuan
de0_Demonstrations
- DE0开发板上的资料,主要是他的例子,含有各种接口程序-DE0 development board information, mainly his example, contain a variety of interface program
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
123
- verilog实现电子钢琴 自己测试过的很好用-verilog for electronic piano with his well tested
Logicos
- Is a Simple andOr, xor, sr circuit on Verilog and his testBench
VHDL
- VHDL语言很严谨，通过对他的学习，编程思维更严谨！这个是很好的VHDL的总结内容，很好对于初学者！-VHDL language is very precise, through his learning, programming, more rigorous thinking! This is a good summary of the contents of VHDL, very good for beginners!
elpiano
- 自己写的FPGA实现电子琴的VHDL程序，曲目是两只老虎，用到一些模块，和片内存储间，-FPGA realization of his keyboard to write the VHDL program, tracks are two tigers, a number of modules used, and on-chip storage room, huh, huh