搜索资源列表
I2CSlave
- Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
i2c_slave_con
- 可以支持连续读写的i2cslave源码，很适合作为master的testbench来用-can support continuous reading i2cslave source, very suitable as a master to the use of testbench
I2Cslave
- i2c slave,这个是I2CBUS接收端的源代码，由VERILOG写成，经过综合和调试
I2Cslave
- 用FPGA作的IIC的收端,文字不够，说点废话-Using FPGA for the resumption of the IIC-side, not enough characters that nonsense point
i2cslave
- 此代码是I2C Slave的Verilog源代码,已经经过上板调试，没问题。-This code is the I2C Slave of Verilog source code, has been on the board debugging, no problem.
i2cSlave_1
- This the first file that describes an i2CSlave interface.-This is the first file that describes an i2CSlave interface.
i2cslave
- i2c slave controller
I2s
- i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-byte registers. These registers can be connected to the users
I2cSlave
- I2C slave, I2C slave,-I2C slaveI2C slave,I2C slave,
i2cSlave
- i2c communication slave module
I2Cslave
- seria l2S convertor to transfer seria ldata