搜索资源列表
alteralvds.rar
- 基于altera系列芯片lvds接口的fpga设计 verilog源码,Series altera-based chip interface lvds source fpga design verilog
xapp866
- 用于 Texas Instruments 模数转换器的 Virtex-4 和 Virtex-5 接口-Texas Instruments ADC for Virtex-4 and Virtex-5 Interface
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
VGA_Controller
- VGA接口图片显示。可以用在DE2开发板上，可以根据AD芯片修改源代码作移植-VGA interface image display. You can use the DE2 board, you can modify the source code under the AD chips for transplant
PCI.rar
- 用VHDL编写的RTL8109与单片机的接口驱动程序.,Prepared using VHDL Interface with MCU RTL8109 driver.
ppt
- 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
ST7565-6800-LCD
- ST7565P 6800接口的驱动程序，有别于网上从多的8080或串口驱动程序。已经验证可以使用。-ST7565 6800 interface driver.have been verified and implemented successfully.
eth_send
- 清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。-Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
HDMI
- HDMI interface verilog code and specificaiton paper
FPGA
- FPGA最小系统的概念组成电路、常用接口和硬件系统的调试-The concept of minimum system composed of FPGA circuits, common interface and hardware system debugging
c_wp260
- 利用 Xilinx FPGA 和存储器接口 生成器简化存储器接口-Using Xilinx FPGA and the memory interface generator to simplify memory interface
mem32_to_pcitarget_verilog
- This design example shows how to implement interface between 32-bit pci target Altera megafunction instantiation and a 32-bit synchronous memory
Verilog-pci
- PCI的FPGA实现，使用verilog硬件描述语言模拟pci数据接口的数据传输过程。-PCI simulation with FPGA, using the verilog hardware describing language to simulate data transfer processes on pci data interface.
FPGA_UART
- FPGA串口实现。 发送和接受数据功能代码-FPGA serial interface. Send and receive data function code
8.4ADC0809
- FPGA中用VHDL编写的AD0809的转换接口电路及程序源码-FPGA using VHDL prepared AD0809 conversion interface circuit and program source code
IDE_Interface
- IDE接口程序，是用VERILOG写的，高手进阶程序-IDE interface program is written using VERILOG, master advanced procedures. .
IDEinterface
- IDE接口时序和最全的接口定义，通过它可以实现硬盘的扇区读写-IDE interface timing and the most comprehensive interface definition, it can be achieved by sector hard disk read and write
SPI
- VHDL语言编写的SPI通信接口,可实现与单片机等外部MCU的通信,且只占用较少的引脚线-Written in VHDL SPI communication interface, can be realized with the microcontroller and other external MCU communication, and only takes less pin line