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project2_verilog
- 简化LAPS协议实现,verilog的大作业。-Simplify the LAPS protocol, verilog great job.
MIPS
- MIPS处理器的组员大作业，可以直接运行，提交，环境是quartus-MIPS processor crew great job, you can run directly, the author, the environment is quartusII
ADC0809VHDL
- 文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Descr ipt
Shortest_job_first
- 短作业优先级算法（在VS2005中，可以自己创建各进程的运行时间，导入后能够运行，）-shortest job first（）
traffic_light
- EDA课程所编的作业——交通灯，具体要求是在道路十字路口的两个方向各设一组红绿黄指示灯，显示顺序为：其中一个方向是绿灯、黄灯、红灯，另一个方向是红灯、黄灯、绿灯；设置一组数码管，以倒计时的方式显示允许通过或禁止通过的时间，其中绿灯、黄灯、红灯的持续时间分别为10S，5S，15S。 -EDA courses compiled job- traffic lights, the specific requirement is that the crossroads on the road in b
exer1
- verilog的大作业题，用Verilog描述一个遥控器，仿真并综合出电路图-verilog big job title, descr iption of a remote control with Verilog simulation and synthesis of the circuit
exer4
- 设计可以对两个运动员赛跑计时的秒表，verilog的大作业 -Design of the two athletes running the stopwatch timing, verilog great job
mimasuo
- 一道作业题目，串行密码锁的设计与实现，希望对大家有帮助-A job title, serial lock design and implementation, we want to help
Goldenguid_Verilog
- Verilog黄金指导（中英文版本）,费了好大劲才找到，发扬共享精神~-Verilog Golden guidance (in English), take a great job finding and carry forward the spirit of sharing ~
Operating_Systems
- The folder includes various algorithms of Operating Systems such as Bankers algorithm,C-Scan,FIFO,Shortest job first,Round Robin etc. All are implemented in C.
paixu
- 给定一个带期限的作业排序问题, n=5, (p1,p2,p3,p4,p5)=(6,3,4,8,5), (t1,t2,t3,t4,t5)=(2,1,2,1,1), (d1,d2,d3,d4,d5)= (3,1,4,2,4), 应用FIFOBB求使总罚款数最小的可行作业集J, 要求:实现对不同作业排序问题实例的求解，问题实例的输入数据存储在case.txt文件中。-Given a scheduling problem with the operation period, n = 5, (p1, p
HARP
- 电子琴，播放音乐，电子通信工程系作业上课作业-Keyboard, playing music, electronic communication engineering job class job
urisc_2011
- 这是一个urisc的作业，用于搭建一个单指令的处理器，-This is a urisc job, build a single instruction for the processor,
ReadFsm
- VHDL小程序，read FSM。可以作为VHDL一次作业使用。包含测试文档testbench。-VHDL applet, read FSM. A job can be used as a VHDL。VHDL code and testbench.
display_combine
- 这是学生做的Verilog HDL 作业。 是一个数字钟。 有时钟，秒表等功能。 原创。-This is the Verilog HDL students to do the job. Is a digital clock. A clock, stopwatch and other functions. The original.
frequency-meter
- 开发环境是quartus ii，是学校的一个FPGA实验，计算一个信号的频率，这个是我做得最好的一个作品，调试成功。压缩包里包含题目要求以及我做好的模块。-Development environment is quartus ii, an FPGA experimental school, calculate the frequency of a signal, this is I' m doing the best work, debugging success. The compres
traffic
- 东南大学信息学院大三编程课，VHDL相关交通灯大作业相关代码。欢迎指教改正-Southeast University, School of Information junior programming class job code for the VHDL traffic lights. Welcome advice corrections
clk_dly
- 用于信息传输时的时钟延时程序，可根据使用情况修改部分内容。-choose a person for a job； make use of personnel； need hands
EDA4--3
- 实现的电子钟，资料非常全面，是一次课程设计的大作业，完成的质量很高。-Achieve the electronic clock information is very comprehensive, curriculum design job, completed high quality.
final
- vhdl语言，实现贪吃蛇功能，whdl大作业……已经调试成功-vhdl language, to achieve Snake function, whdl big job ...... debugging has been successful