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wavefetch
- ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看，也可以将比较的结果生成一个文本文件-ModelSim waveform can be compared to the current functional simulation with a reference (WLF paper ), the results can be compared in the waveform window or window List
wishbone_i2c_master
- -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 200
List.3DS-Proteus-ARES
- 3D Model to Proteus/ARES 3D PCB Visualization
manchester_verilog
- 采用Verilog HDL语言编写的曼彻斯特码， 文件列表： help md.v md_tf.v me.v me_tf.v med.v-Using Verilog HDL language of the Manchester code, the file list: helpmd.vmd_tf.vme.vme_tf.vmed.v
EDA
- 设信号ＣＨ表示计算路程脉冲，每０.１公里变化一个周期．出租车三公里内为起步价７.０元，超过三公里，每公里２.４元．设置一个开车键，停止状态按动一次表示开车，开车状态按动一次表示下车．一个暂停键，暂停是停止收费，再次按动继续收费．七段码显示当前价格和路程．且所有七段码为动态显示． 如果有谁会的话，帮帮忙吧，写些主要的程序就行了-Established that the calculation of CH distance signal pulse, 0.1 kilometers of each
fpga_sec
- 学习使用波形比较功能的基本方法,ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看，也可以将比较的结果生成一个文本文件-Learning to use the wave function of the basic method of comparison, ModelSim wave function can be compared with a reference current simulation (WLF fil
coslist
- cos表值寄存器，1024点，10位地址，10位数据-the list of cos，1024 points，10 bits of address, 10 bits of data
ARM
- ARM内核及性能比较(列表对比)包含arm7、arm9、arm9e、arm10e、arm11等-ARM core and performance comparison (list comparison) contains arm7, arm9, arm9e, arm10e, arm11, etc.
firewire
- test former partlelr list
s3_bom
- sparten开发板的bom清单，相当详细，各元件的详细描述-sparten bom development board list, very detailed descr iption of each component
barrons-word-list
- barrons word list very useful
50973937-VHDL-Report
- Introduction This report is organized as following.First, it is divided into chapter 2 to chapter 12. Within each chapter, VHDL code is presented at the beginning of each problem. Then, simulation results for these codes is also included. For s
Example-4-8
- always模块的敏感表为电平敏感信号的组合逻辑电路 这种形式的组合逻辑电路应用非常广泛，如果不考虑代码的复杂性，几乎任何组合逻辑电路都可以用这种方式建模。always模块的敏感表为所有判定条件和输入信号，请读者在使用这种结构描述组合逻辑时，一定要将敏感表写完整。在always模块中可以使用if…else…、case、 for循环等各种RTL关键字结构 assign等语句描述的组合逻辑电路 这种形式的组合逻辑电路适用于描述那些相对简单的组合逻辑，信号一般被定义为wire型，常用
FPGA-logic-design-considerations
- FPGA逻辑设计注意事项， 这是一个在逻辑设计中注意事项列表，由此引起的错误常使得设计不可靠或速度较慢，为了提高设计性能和提高速度的可靠性，必须确定设计通过所有的这些检查。-FPGA logic design considerations, this is a note in the list of logical design, which often makes the design errors caused by unreliable or slow, in order to impro
dianziqin
- 详细列举了电子琴的功能和作用，通过VHDL软件设计的方法方真出其结果，对于提高VHDL有很大的帮助-Keyboards list in detail the functions of the software design, the method by VHDL true out its results, party for improving VHDL has very great help
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
spi_cpld_vhdl
- The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified to support other families of S
_7_seg7x8_dynamic_disp
- Seg7x8_dynamic_disp seg7x8动态显示 （1）源代码 seg7x8.v seg7x8_drive.v （2）管脚分配 pings list.txt -_7_seg7x8_dynamic_disp Dynamic display (1) source code seg7x8.v seg7x8_drive.v (2) pin assignment pings list.txt
_1_turn_on_led
- verilog实例 点亮LED[1]、LED[3]、LED[5]、LED[7] （1）源文件 turn_on_led.v （2）管脚分配 pins list.txt -verilog实例 点亮LED[1]、LED[3]、LED[5]、LED[7] （1）源文件 turn_on_led.v （2）管脚分配 pins list.txt
_2_sw_led
- verilog实例2 sw_led 使用拨动开关控制LED亮灭 （1）源文件 sw_led.v （2）管脚分配 pins list.txt -2 sw_led 使用拨动开关控制LED亮灭 （1）源文件 sw_led.v （2）管脚分配 pins list.txt