搜索资源列表
sopc
- altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
I2C_1.1
- Simple I2C controller -- 1) No multimaster -- 2) No slave mode -- 3) No fifo s -- -- notes: -- Every command is acknowledged. Do not set a new command before previous is acknowledged. -- Dout is available 1 clock cycle later as cmd_a
BoothMultiplier
- -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthe
wave_gen
- 波形发生器，带TESTBENCH， 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH.
chengxufengxiang
- 这些程序我用MAX+PlusII软件测试均能通过编译，程序本身不复杂，旨在为刚接触VHDL语言的朋友提供一些样例，以便了解VHDL语言的基本构成。如果要运行测试，则新建文件名应于程序中实体名一致，文件后缀“.vhd”，不推荐直接通过复制、粘贴的方法录入程序，可能会引入错误字符。 -these procedures I used MAX PlusII Software Testing pass compiler, the process itself is not complicated. for
steppermotorVHDL
- 一种全新的VHDL控制步进电机驱动代码，以供学习-a new VHDL controlled stepper motor driver code for learning
AvalonPwm
- SOPC实验--Hello World实验:启动Quartus II软件，选择File→New Project Wizard，在出现的对话框中填写项目名称 2、 点击Finish，然后选择“是”。选择Assignments→Device，改写各项内容。Family改为CycloneII，根据实验板上的器件选择相应的器件，本实验选择EP2C5T144C8,点击对话框中的Device & Pin Options，在Configuration中，选项Use Configuration Device为E
verilog2000
- verilog2000更新部分，请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support
FPGA控制VGA显示（Verilog）
- 用FPGA开发板控制VGA显示，以800*600的分辨率，首先在屏幕的正中央依次出现“新”“年”“快”“乐”四个汉字，并分别移动到屏幕的四个角落，接着在屏幕中部从左至右依次出现“Happy New Year”英文字样，然后出现三个由小到大再消失的圆形图标模拟烟花，最后在黑屏中闪烁金星。字体均采用不同颜色，增添喜庆气氛。 本代码是练习VGA控制，ROM调用，时序控制及状态机运用的一个综合实例！
VHDLToVerilog.rar
- VHDL实例，小小的一个试验例子，希望对新手有帮战,VHDL example of a small example of a pilot, I hope there is help on the new war
create_new_component
- sopc 中，新建component。详细介绍了如何根据HDL代码生成黑盒的过程。-SOPC, the new component. Described in detail how the HDL code generation black-box process.
VHDL.2008.Just.the.New.Stuff
- A new book on new vhdl standard "VHDL-2008" by peter ashenden
vhdl-2008-just-the-new-stuff-systems-on-silicon.r
- VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL
a-new-digital-PLL
- 基于FPGA实现的一种新型数字锁相环设计。该设计是用VHDL来实现的，个人觉得不错，所以传上来和大家分享-FPGA-based implementation of a new digital PLL design. The design is to use VHDL to implement the individual feels good, so come and share transfer
a-new-mthod-of-cic3_decimator
- 一种CIC滤波器的实现方法，包括以下步骤：将数据信号输入一梳状滤波器组进行滤波，所述梳状滤波器组由若干梳状滤波器级联而成；将滤波后的数据信号输入一保持器；将保持器输出的数据信号经一积分器组输出，所述积分器组由若干积分器级联而成，与所述梳状滤波器组的级数相同。一种CIC滤波器，包括：梳状滤波器组，由若干梳状滤波器级联而成；积分器组，由若干积分器级联而成；保持器，串联在最后一级梳状滤波器的输出端和第一级积分器的输入端之间。-a new method of CIC
Whats-New-in-CORE-Generator-and-IP
- ise13.1中有什么新的ip核和资源，希望用ise的朋友能好好看看。-ise13.1 What' s new in the ip nuclear and resources in the hope that friends can have a good look at ise.
A-Branch-Predictor-with-New-Recovery-Mechanism-3.
- A Branch Predictor with New Recovery Mechanism
New-Verilog-2001-Techniques-for-Creating-Paramete
- New Verilog-2001 Techniques for Creating Parameterized Models
Optimized-reversible-BCD-adder-using-new
- Optimized reversible BCD adder using new
happy new year
- 利用硬件板子上的蜂鸣器实现的新年快乐的歌曲(Using the buzzer on the hardware board to achieve a happy New Year's song.)