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35_486_bus
- 请注意： 本例的源描述包含文件类型，在学习版上不能编译及模拟， 如果您需要对此描述进行编译及模拟，请与北京理工大学 ASIC研究所联系。 另外，此例与第75例是同一个电路的不同部分的描述，可以 一起参考这两个例子的描述。-Please note : The cases include the descr iption of the source file type, version of the study can not be compiled and simulation, if
USB IPcore（带说明）
- USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
44vhdl
- 44个vhdl实例 注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I / O exte
digitalinterfaceuart
- 文件说明了在fpga/cpld中怎样实现数据接口及其实例了urat-note of the document they simply / cpld How Data Interface and the examples of urat
clock_CPLD
- 采用MaxPlusII写的一个小时钟程序，也是供初学参考。呵呵。注///版主，开发环境里面没有MaxPlusII.-MaxPlusII used to write a small clock procedures, as well as reference for beginners. Ha ha. Note / / / moderator, development environment there's no MaxPlusII.
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
I2C_altera
- I2C的说明!基于FPGA的I2C总线控制核设计,大家帮忙-I2C Note! FPGA-based nuclear I2C bus control design, we look at the help
shejiVerilogExample
- Verilog 程序例子 王金明：《Verilog HDL程序设计教程》程序例子，带说明。 -Verilog procedures guo examples : "Verilog HDL Design Guide" procedures example, take note.
cordic
- cordic算法的vhdl实现，内附有文档说明-cordic algorithm vhdl realized, a document containing a note
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
Alu1232
- VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue
sdram4m16_L2_42
- 用FPGA实现SDRAM的操作，具体操作见内部说明文件-FPGA SDRAM with the operation of the specific see internal note
三种16位整数运算器的ALU设计方法
- 三种16位整数运算器的ALU设计方法，调用库函数74181（4位ALU），组成串行16位运算器。(用74181的正逻辑) B．调用库函数74181和74182，组成提前进位16位运算器。(用74181的正逻辑) 注意：调74181库设计，加进位是“0”有效，减借位是“1”有效，所以最高位进位或借位标志寄存器要统一调整到高有效 C．用always @，case方式描述16位运算器。,Three 16-bit integer arithmetic logic unit of the ALU
ds18b20.ds18b20的Verilog程序
- ds18b20的Verilog程序，经测试验证可以使用。注意此版本为DALLS DS18B20而不是DS1820,注意加5K上拉电阻。,ds18b20 the Verilog process can be used to verify by testing. Note that this version rather than DALLS DS18B20 for DS1820, the attention of Canadian 5K pull-up resistor.
AN151
- AMBA Application Note: AN151 - Using EB with example AXI Logic Tile. -AMBA Application Note: AN151- Using EB with example AXI Logic Tile. This example shows how to use the EB baseboard with an example AXI Logic Tile. The following board c
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
s
- 基于VHDL的选择运算器，可以通过选择端选择加减与或四种运算，每个时钟周期刷新结果一次。注释已给出。-The choice of VHDL-based computing device, you can choose by selecting the side addition and subtraction with or four kinds of operations, the results of one per clock cycle refresh. Note has been gi
The-Specification-of-SDC
- 综合约束文件SDC的写法说明 synopsys 出品-Using the Synopsys Design Constraints Format Application Note
CRC-Application-Note
- 赛灵思官方发布的关于CRC（循环冗余校验）的设计指导书，对想利用硬件描述语言编写CRC代码的同志很有帮助-CRC Application Note from Xilinx
fpga-learn-note
- fpga学习资料文档，主要是用于数字信号设计，支持下载-fpga learn note