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(7.27)final_cbb01
- 网络中交换节点的上数据的交换和下行数据分发的硬件实现-network nodes to exchange data on the downlink data exchange and distribution of hardware
2Dfft
- VHDL 关于2DFFT设计程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-mo
verilog-som
- 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
fpga-dm9000a
- 一个项目工程，硬件包含XINLINX FPGA，配置FLASH，串口，SDRAM,与以太网芯片DM9000A，实现数据采集，以太网传输，电路验证完全正确，请放心使用，SPARTAN 3E 的BGA引脚320个，不容易布板，可以参考使用的。要FPGA实现网络通信也可以参考电路，B因为产品升级了所以公开原来的电路的。 -A project engineering, hardware contains XINLINX FPGA, configuration FLASH, serial port, SD
eth_send
- 清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。-Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.
DE2_NET
- 基于altera公司EP2C35672C6的DE2板子的光盘中的自带文件。DE2_NET，网络模块。-Based on the DE2 board altera company EP2C35672C6 CD in its own file. DE2_NET, network modules.
netfpga_full_3_0_0.tar
- 斯坦福大学的netfpga最新源代码开发包，用于开发网络路由器交换机等-Stanford University netfpga the latest source code development kit for developing network switches routers
s3en_udp
- 基于spartan3e开发板嵌入式EDK开发的UDP协议网口开发程序-EDK embedded development board based on spartan3e UDP protocol developed network port development program
lvpecl_connect_lvds
- 在FPGA间实现LVDS和LVPECL互联时的用法，比如如何做匹配网络-Achieved in the FPGA LVDS and LVPECL interconnection between the time of usage, such as how to do the matching network
Verilog_SOM
- Verilog编写的SOM(自适应神经网络算法)-Verilog written SOM (self-adaptive neural network algorithm)
nerualnetwork
- 本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。 -In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.
mesh_dft
- 自己写一个关于维mesh结构的noc网络，verilog，仿真结果无误。-Write their own structure on the noc-dimensional mesh network, verilog, accurate simulation results.
CPU_Architecture
- Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common netw
B_PON_OLT_VHDL
- ATM-PON(Passive Optical Network) OLT vdhl proj.file
4by4
- 4输入，4输出，clos网络所用，有利于连接处理器和处理器，处理器和存储器传输数据。-4 inputs, 4 outputs, clos network use is conducive to connecting the processor and processor, processor and memory to transfer data.
MLP-network-prior-t-th-FPGA-implementation
- 前向MLP网络的FPGA实现MLP network prior to the FPGA implementation-MLP network prior to the FPGA implementation
Zoom-forward-a-relay-relay-network
- 放大转发中继网络中的一种中继选择方案 放大转发中继网络中的一种中继选择方案-Zoom forward a relay relay network relay option to enlarge the network to forward a relay option
ANNs
- 人工神经网络（ArtificialNeuralNetworks，简写为ANNs）也简称为神经网络（NNs）或称作连接模型（ConnectionistModel），它是一种模范动物神经网络行为特征，进行分布式并行信息处理的算法数学模型。这种网络依靠系统的复杂程度，通过调整内部大量节点之间相互连接的关系，从而达到处理信息的目的。 -Artificial neural network (ArtificialNeuralNetworks, abbreviated as ANNs) also refe
A-Network-based-Telemedicine-Service-6
- A Network-based Telemedicine Service
the-Application-of-FPGAs-for-network
- Summerville写的FPGA在大型网络设备中的具体应用-Summerville write the FPGA in the large network equipment