搜索资源列表
clock24
- 这是一个数字时钟的Verilog程序 仿真通过 能实现秒 分 时 计时-This is a digital clock Verilog simulation process can be achieved through the TDM time seconds
tdm_latest[1]
- TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换-TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange
ARM_Core
- 国外网站下载到的，ARM7的TDM核，VHDL编写-The vhdl source code of TDM core from by using ARM7
TDM
- 运用VHDL实现十分多路复用，毕业设计来的，很清楚 ，希望对大家有用-matlab in Applied Communication Theory, TDM emulation, hope that we can useful!
TDM
- 利用时分复用技术将并行输入的四路八位二进制码的信号变成一路信号串行输出(TDM digital multiplex VHDL)