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uart-TO-SPI-FLASH-20130226
- 代码实现了电脑向uart 发送四个字节(命令1字节 地址3字节)然后 对M25Pxx系列的芯片进行任意地址的读写, 目前只实现单字节默认数据的读写!有需要的可以 修改-uart to spi control the M25PXX IC
uart
- UART模块的verilog代码,经过测试,能够实现正常的接收和发送功能。-Verilog code for UART module has been tested, it is able to achieve normal receive and transmit functions.
uart
- uart的Verilog代码,经过测试没有问题,有测试文件-uart Verilog code, no problem tested, the test file
uart-in-verilog
- develop uart using verilog language-develop uart using verilog language...
UART
- 本论文使用Verilog HDL 语言描述硬件功能,利用QuartusII 5.0在 FPGA 芯片上的综合描述,采用模块化设计方法设计UART(通用异步收发器)的各个模块。-The paper using Verilog HDL language to describe hardware features, the use of the FPGA chip QuartusII 5.0 comprehensive descr iption of the modular design approa
Verilog-UART
- 功能:UART串口通讯实信实验 描述:本程序共四个模块 模块1:接收数据的波特率发生模块,接收模块在接收到下降沿时,通过标志位启 动该模块的波特率计数器,并在计数中返回一个采样标志位给接受模块, 通知接收模块采样; ---------------------------------------------------------------------- 模块2:数据接收模块,该模块一旦监测到数据输入端有下降沿,就立即启动波 特率(标志位置1),并使
uart
- 利用verilog实现与uart的通信,uart接口-uart interface realize
uart-project
- uart verilog zzpoifeow fwpoep wf wpo fpw pdfikwpoe e opfewiepfow [efkpow f pkw[fpkdw[kef[w fkepowkf[ok[ew f[pekwp fpoefi[wie-UART verilog
UART-by-Verilog
- 用Verilog实现UART,并且附有详细说明那个-The Verilog UART, and with the detailed descr iption that
verilog-uart-rs232
- verilog HDL 描写的uart程序 由PC端接收然后+1返回 等等 东南大学09级4系综合课程设计-verilog HDL descr iption uart program Received by the PC side and then+1 back。 SEU..
uart
- uart source code using vhdl
uart
- VHDL编写的UART异步串行通信接口程序,,,经过仿真验证,简单易懂-VHDL prepared UART asynchronous serial communication interface program, through simulation, simple,,,,,
UART-finite-state-machine
- 基于Verilog语言的,用有限状态机实现Uart,很实用-UART design based on finite state machine
uart
- 基于wishbone的 uart 通信设计-The uart communication design based wishbone
uart
- 一个实用的uart协议模块,使用verilog 实现-A practical uart protocol modules, use verilog to achieve
uart
- 用verilog写的程序实现串口通信, 用verilog写的程序实现串口通信, -the program is based on verilog, and it s fuction is comunicate with uart
UART-FPGA
- verilog的UART通信,解决了接受过程中的毛刺问题,将接受和发送两个过程独立开来-The UART verilog communication, solve problems receiving glitches during the process of receiving and sending two separate open
Fix-data-send-UART
- Fix data UART send and receive verilog codes.
UART
- FPGA Verilog UART 通信源代码-FPGA Verilog THIS IS A UART SQC
uart
- Verilog,实现Uart的收、发功能-Verilog, achieve Uart the sending and receiving functions