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uart from opencores
- 用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
H16550_2[1].0V
- 专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550 ，包含完整的使用说明手册、testbench、可综合，如果被网站认可，将继续上传其余的几个更好的core。-specialized processor and peripheral interfaces famous ipcore CAST product manufacturers UART H16 550, including full use manual testbench can be integrate
uart2
- uart 通用异步接受机 编译环境为quartus-UART Universal Asynchronous Receiver and build environment for Quartus
URAT_VHDL
- URAT VHDL程序与仿真 各程序运行环境为MAXPLUS_-UART procedures and VHDL simulation environment for the operation of the procedures for MAXPLUS_
ISE_uart
- 自己在ISE下用VHDL写的UART，简单，易懂-in ISE using VHDL was the UART, simple, understandable
vhdl-2
- UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
Exp6-VGA
- 通过UART从PC主机读取图片数据，并完成图片在VGA显示器上的显示-through UART from the host PC to read image data, and complete picture of the VGA display on the show
USBXilinx
- 实现了串行通信接口的全部功能，符合RS-232-C标准的完整UART模块源代码，中文注解，清晰易懂，经过严格仿真测试，绝对好用。-a serial communication interface of all functions, with RS-232-C standard UART modules complete source code, Chinese notes, lucid, after a rigorous simulation tests, absolutely useful.
Receiver_spartn6_v1
- Implement design of UART receiver in verilog
uart_design
- UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
UART_FPGA
- FPGA下的UART串口通信协议及控制器设计(UART serial communication protocol and controller design under FPGA)
PC2FPGA_UART_Test
- 基于 fpga 的 uart 设计 波特率 115200(UART design based on FPGA)
uart
- 实现串口的收发，可以稳定的运行，经过测试，可以完全应用于项目中。(The implementation of the serial port and transceiver, can run stable)
uart_rx
- Verilog实现的RS232发送和接收程序，有完成的verilog代码，testbench等。(UART send and receive verilog code, including verilog source code, testbench etc.)
teacher_uart
- 由verilog编写的uart收发模块，能够在串口助手发送字符，并在数码管上显示，开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)
VerilogUart_Modelsim
- 使用Verilog编写的UART ，用Modelsim仿真工程。(use Verilog Write UART Program, Modelsim simmulate the project)
uart
- 电脑端发送数据与FPGA接收数据程序，uart模块，以及一部分项目里包含的其他的程序(Program for sending data from computer and receiving data by FPGA, UART module)
UART串口工程
- UART串口工程，RS232串口，实测可以使用，可以用来学习学习
国产FPGA参考设计IPCORE_UART_example_M5&M7
- 国产FPGA的UART参考设计IPCORE源代码。 The IP provides two kinds of simplified interface connected to EMIF bus and AHB bus for communication with 8051 core and ARM core.The two kinds of interface are full-duplex serial communication interface. Support programmabl