用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs,

cyclone的pll应用，精确翻译，适合需要又不想看英文文献的同学。-cyclone the pll applications, accurate translation, suitable for students of English literature need not want to see. Undo edits Dictionary