搜索资源列表
VHDL.fifo
- 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
UART.使用FPGA的FIFO，状态机
- 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。,The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
fifo
- 先进先出存储电路fifo，实现队列存储结构-xianjin xianchu chunchu dianlu fifo
mem_ctrl_latest.tar
- 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
FIFO
- 异步FIFO的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
fifo
- 此程序为存储器常用的FIFO（先入先出），程序中没有指明位宽，这样更适合于初学者进行套用-This process commonly used for the memory FIFO (FIFO), the procedure is not specified bit, so more suitable for beginners to apply
Fifo
- 一个FIFO源代码，基于Altera FPGA-A FIFO source code, based on Altera FPGA
FIFO
- 一个用VHDL源码编写的先进先出(FIFO)缓冲器模块.可以进行FIFO的仿真验证-A source prepared by VHDL FIFO (FIFO) buffer module. Can verify FIFO simulation
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
connect20090223
- fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
fifo-interface
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
FIFO
- 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
fifo
- 用VHDL语言写的FIFO代码，可设FIFO的深度-VHDL language with code written in FIFO, FIFO depth can be set up
FIFO
- This code is a FIFO memory vhdl developed in ISE Software
fifo_vhdl
- FIFO的VHDL编程，其中包括FIFO的读，写，满帧，半满帧信号驱动-FIFO of the VHDL programming, including the FIFO' s read, write, full frame, half-full frame signal drive
fifo
- fifo 的vhdl源程序,容量为1024*8的fifo程序代码-fifo the vhdl source code,Capacity of 1024* the fifo code 8
fifo
- 同步FIFO 创建一个256x8大小的同步FIFO，并通过串口发送数据初始化FIFO，FPGA内部读取FIFO的数据通过窗口发送到PC-FIFO