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top6
- fpga2分屏代码，实现dvi输入视频信号，双路dvi输出视频信号，完成1分2-fpga2 split-screen code to achieve dvi input video signal, dual dvi output video signal, completed 1 of 5
DE1-verilog
- Altera公司推出最新开发板DE1。该资料为DE1的FPGA 代码，包括ADC，音频处理，视频输出等，供大家参考使用。-Altera Corporation introduced the latest development board DE1. The data for the DE1 FPGA code, including the ADC, audio processing, video output, etc., for your use and reference.
videocpt
- 用VHDl语言实现高速视频数据采集模块代码-High-speed video data acquisition module code language used VHDl
caiyang
- 数字视频光端机发送端采样过程编码二十字有木有-Digital Video Optical sending end sampling procedure coding
DE2_video_pass_demo-rww
- 视频发射源发射信号，基于DE2115fpga平台的视频信号显示与处理-Transmitting the video signal transmission source, based on a video signal display DE2115fpga platform and processing
IMAGE_0424
- FPGA实现视频图像实时缩放功能 QUARTUS环境下测试成功-FPGA to achieve real-time video image zoom feature
DE2_70_D5M_XVGA
- 针对DE2修改的工程文件，可以正常输出1280*1024的视频图像，并且可以自行进行源码的修改-For DE2 modified project file, it can output 1280* 1024 video image, and modify the source code can be
sdram_ov7670_rgb_vga_640480
- ov7670摄像头工程源码，使用的是黑金开发板，摄像头正常输出640*480的视频图像，对开发人员有很好的参考价值-ov7670 camera project source code, using the black gold development board, camera normal output of 640* 480 video images, the developers have a good reference value
rs_decoder_31_19_6_latest.tar
- 31.19解码器- RS code is the BCH code of multi-systerm, after a long time of development, the theory and technology of RS code has been rather mature that it can rectify burst error and random error at the same time, especially burst error. It is widel
bt1120p_gen
- bt1120时序生成，verilog程序，1920x1080p60分辨率-synchronized video timing generation itu bt1120 within verilog program, 1920x1080p60 resolution
vmodcam-ref-hd-demo-12
- 通过fpga控制从vmodcam中获取视频数据并通过vhdmi发送到显示屏上-And sent via fpga control access to video data from vmodcam on display through vhdmi
vmodcam-ref-hd-demo-13
- 通过fpga控制从vmodcam中获取视频数据并通过vga发送到显示屏上2-Fpga control access to video data from vmodcam and send to the display via vga 2
yuvbt1120
- 采集不同分辨率视频，输出相同视频，实现bt1120编码，iic与arm通信-Different resolution video capture and output the same video coding to achieve bt1120, iic communicate with arm
Calculator
- VHDL计算器，涉及PS2输入，VGA视频输出，加法器，BCD转化。可以通过研究代码学习以上知识-VHDL calculator, involving PS2 input, VGA video output, the adder, BCD transformation. You can learn more knowledge through research code
4.-VGA-graphic-mode
- VGA (video graphics array) is a video display standard introduced in the late 1980s in IBM PCs and is widely supported by PC graphics hardware and monitors. We discuss the design of a basic eight-color 640-by-480 resolution interface for CRT (c
submit
- 用VHDL实现的双人飞机大战。支持PS/2和蜂鸣器。 需要两个CPLD核心协同完成。 含最终效果视频-Multiplayer air fight implemented in VHDL. PS/2 and beeper supported. Two CPLD cores are required to run this demo. Final video includes.
DE2_NIOS_HOST_MOUSE_VGA
- 本代码为DE2开发板例程源码（EP2C35F672C6），项目基于quartus II 9.0（随板光盘为7.2版本以下，在9.0版以上编译会报错）。本项目实现一个USB画笔功能，通过FPGA控制USB口，USB口接上鼠标，通过XGA口外界显示设备，实现显示设备对鼠标移动轨迹的显示。-In this demonstration, we implement a Paintbrush application by using a USB mouse as the input device.This
DE2_TV
- 本代码为Altera DE2开发板例程源码，（FPGA：EP2C35F672C6）quartus II 9.0以上可以编译（随板源码为7.2以下版本，在9.0以上版本编译会报错）。本代码实现一个音视频播放器TV_BOX。-This demonstration plays video and audio input a DVD player using the VGA output and audio CODEC on the DE2 board. There are two major bl
OV7670_VGA
- 采用OV7670摄像头采样视频数据通过FPGA DE2开发板用VGA显示在显示屏上。-Using OV7670 camera video data sampled by FPGA DE2 development board with a VGA display on the screen.
bt656_timing_analysis
- BT656信号分析参考规格书，对分析bt656信号非常有帮助-The video standard ITU-R.656 timing analysis