搜索资源列表
verilog SDRAM core
- 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
verilog
- verilog设计练习进阶,针对的读者是 verilog hdl的初学者。
verilog
- 北大微电子学系于敦山老师的课件,介绍Verilog HDL、Cadence Verilog仿真器、可综合的Verilog HDL、设计举例、自动布局布线工具、Verilog的词汇约定等内容
verilog
- 小例子,关于Verilog HDL语言的一些小练习,可供参考.
verilog
- 是几个用Verilog HDL语言编写的源代码(里面包括实现滤波器等),对想学习这个语言的朋友很有帮助!
Verilog HDL Examples
- verilog的入门级别的例子(转载)-Verilog entry-level examples (reproduced)
add.rar
- 流水线乘法器与加法器 开发环境:Modelsim(verilog hdl),Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
viterbi.rar
- 这是一个用VERILOG HDL语言编写的viterbi译码程序,This is a language VERILOG HDL by the viterbi decoding process
4NandFlash.rar
- 基于verilog hdl 的Nand Flash控制代码,Verilog hdl-based control code of the Nand Flash
sWave.rar
- 正弦波,Verilog波形发生器,很好的东西,Sine wave, Verilog waveform generator, a good thing
AHBtoAPB.rar
- amba总线桥:ahb to asb!verilog hdl文档加代码,非常全,soc,amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
verilog
- 基于FPGA的LCD12864驱动显示程序 verilog hdl编译已通过 -LCD12864 Show verilog hdl compiler
CAN_IP.rar
- 这是CAN总线控制器的IP核,源码是由Verilog HDL编写的。其硬件结构与SJA1000类似,满足CAN2.0B协议。,This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
VerilogHDL44keyboard.rar
- verilog hdl 4*4 矩阵键盘,去抖,verilog hdl 4* 4 matrix keyboard, to tremble
DDS-top.rar
- 能够基于DDS实现输出正弦波形的一部分程序,利用Verilog HDL语言编写。,Able to achieve based on the DDS output sine wave-shaped part of the procedure, the use of Verilog HDL language.
DDC.rar
- verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用,好用。,Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
Verilog.rar
- verilog HDL 4×4矩阵键盘驱动程序包括硬件电路图,verilog
demodulation
- 基于verilog HDL的BPSK解调的FPGA实现,仿真结果验证良好。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684BPSK u89E3 u8C03 u7684FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u826F u597D u3002IDE u4E3Avivado 2014)
Verilog HDL
- 2015年全国电子设计大赛F题,时间间隔测量模块,占空比测量模块,ISE编写的verilog程序。(2015 national electronic design competition F title, time interval measurement module, verilog program written by ISE.)
Verilog数字VLSI设计教程(源码)
- Verilog 数字VLSI 设计教程 官方Lab(Verilog Digital VLSI Design Course Official Lab)