搜索资源列表
gcd
- 欧几里得算法求最大公约数电路的Verilog实现，消耗功率较低-Euclid algorithm for the realization of the common denominator Verilog circuit, lower power consumption
gcd
- 这是一个求最大公约数的verilog源码-this is a verilog source code which can count the greatest common divider .
VHDLvsVerilog
- This document is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their differences. The second part contains a worked example of a model that computes the Greatest Common Divisor
GCD
- Verilog 最大公约数设计RTL级代码和芯片设计图-Verilog GCD Design and synthesis layout
gcd3
- 用verilog代码编写的GCD即找两个数之间的最大公约数的FPGA工程。-Verilog code written with the GCD of two numbers that find the common denominator between the FPGA project.
gcd_performence
- 基于流水线设计的性能优先的gcd算法的verilog 代码 频率可达500M-based pipeline design gcd for high clock
GCD_Verilog
- 利用Verilog语言写的采用更相减运算的球两个数的最大公约数-Using Verilog language written using a subtraction ball number two of the greatest common divisor
Verilog-code-for-finding-GCD
- State machine implemented in verilog to find GCD of two 8 bit numbers. Two files are included (module and its testbench)
lowpower
- 最大公约数（GCD）stein算法实现，低功耗状态机实现(The greatest common divisor (GCD) stein algorithm, low power state machine implementation)
highperformance
- 最大公约数（GCD）stein算法实现，高性能流水线实现(The greatest common divisor (GCD) stein algorithm, high performance pipeline implementation.)