搜索资源列表
ds180_7Series_Overview
- 赛灵思7系列的FPGA的概览PDF，官方原版文档，没有进行任何修改以及注释。供大家下载参考-Xilinx 7 Series FPGA overview PDF, official original document, without any modifications and comments. For you to download reference
dsp_core_tx_filter
- 应用在USRP N210上的XIlinx的FPGA开发板上面的变采样滤波器，实现25--30.72M的变采样滤波器，适应LTE物理层的要求-Application on the USRP N210 FPGA development board above XIlinx variable sampling filter, to achieve 25- 30.72M variable sampling filter, adapt LTE physical layer requirements
20131010-code
- fx2lp 68013 xilinx XC3s400 实现slave fifo通讯，包括68013的固件以及fpga的代码（verilog）。摸了好久才调试通过的，特共享出来解救苍生！-fx2lp 68013 xilinx XC3s400 slave fifo
AN_KIT_RS232
- 采用C语言在Microblaze下开发的FPGA程序，适用于Xilinx Spartan3AN 开发板-Using C language in Microblaze FPGA development program for Xilinx Spartan3AN development board
ISE_lab1
- 基于Xilinx公司Spartan 3E fpga,实现入门工程的建立，波形仿真，及下载VHDL程序，以及简单门级电路的设计-Based on the Xilinx Spartan 3E fpga, to achieve the establishment introductory engineering, simulation waveforms, and download VHDL procedures, and simple gate-level circuit design
FRFT_Ozaktas
- 这是分数阶傅里叶变换FRFT的土耳其算法的FPGA实现的程序，FPGA是Xilinx的virtecx-5，这是我在做毕业设计的时候自己编写的，希望能对你有帮助！-This is the fractional Fourier transform algorithm FRFT Turkish FPGA implementation of the program, FPGA is the Xilinx virtecx-5, which is what I was doing graduate desi
VGA.doc
- 用vhdl实现横竖彩条纹的显示，通过xilinx仿真软件生成bit文件，下载到fpga开发板上-Horizontal and vertical stripes using vhdl color display, generate bit file by xilinx simulation software, download it to fpga development board
Mold-sixty-counter
- 基于FPGA的模六十计数器设计。在xilinx上运行。-FPGA-based design mold sixty counter. Runs on xilinx.
bmd_design
- 基于XILINX VC6LX550T FPGA开发的xapp1052即DMA传输验证程序，接口部分的管脚绑定可根据自身芯片型号进行修改-Verify that the DMA transfer process, pin binding interface part can be modified based on XILINX VC6LX550T FPGA development according to its own chip models xapp1052
filter_2d
- XILINX ISE FILE FOR FPGA IMPLIMENTATION OF 2D FIR FILTER USING MODIDIED BOOTH ALGORITHM
evodem_mppt_son_hali_OK
- This my complete simulink project using xilinx system generator blocks. There is a buck converter and a control unit for FPGA calculating MPPT to get maximum power from the PV panel. MPPT calculation is done using sysgen blocks. Also HWCOSI
pg054-7series-pcie
- 赛灵思 7系列pcie设计，官方参考资料-xilinx 7 series FPGA PCIe design， reference
fpgahdl_xilinx-edk.tar
- xilinx zynq 7000 FPGA demo-xilinx zynq 7000 FPGA demo
ball_game
- VHDL VGA 弹球游戏 基于Xilinx Spartan 3E的FPGA 通过VGA显示弹球游戏-VHDL VGA pinball game is based on Xilinx Spartan 3E FPGA pinball games via VGA display
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
monitoringV5
- 文件的FPGA是基于Xilinx ISE写的，所用开发板为zedboard7020 484系列，完成的功能为：读取XADC里的温度，VCC，并存储到RAM中，通过流水灯实现翻看，读取等功能.-Document is based on Xilinx ISE FPGA wrote, the use of development board for zedboard7020 484 series, completed functions: reading XADC in temperature, VC
TP_13_12_2013
- Un ensembles des applications réaliser sous SDK xilinx pour FPGA Spartan 3E
Ecar
- 基于FPGA的一个小游戏，在VGA上实现赛车游戏,开发版型号为ANVYL燧石，在Xilinx ISE环境下编译-An FPGA-based games, racing games on the realization VGA, Developer Edition model ANVYL flint, compiled under Xilinx ISE environment
1540000000000031952_taxi
- 一个基于FPGA使用VHDL语言编译的出租车计价器，在Xilinx ISE环境下编译-An FPGA using VHDL language compiler taxi meter, compiled under Xilinx ISE environment