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Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
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xilinx fpga 做VGA驱动信号的Verilog原代码,ise版本9.2,,xilinx fpga do VGA driver signals Verilog source code, ise version 9.2,
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ADC0832是一个8-bit的ADC转化芯片，工作频率为250Khz，最大频率可达400Khz，转化通道有两个，输入电压可分有单端或差分形式。本测试使用单端电压输入形式，从昔年的CH0输入电压，使用Xilinx XC3S200AN开发板，并且使用Xilinx ise工具中的ChipScope工具来查看转化后的DO数据是否正确。经验证，输入电压范围是0V--5.5V,当电压达到5.5V时，满刻度.,ADC0832 is an 8-bit conversion of the ADC chip, t
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mac控制器ip核，语言verilog,开发环境xilinx ise,quartus ii等
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It s a design of a 4*4 multiplier based on Verilog, using Xilinx ISE.
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载波频率同步Verilog程序 基于xilinx ise 实现-Carrier frequency synchronization Verilog program is based on xilinx ise to achieve
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this Code is in verilog HDL.
This Code is for piplined processor with 4 opcode.
this will work in three cycle latch, decode and exicute..
test bench for xilinx ise is laos given
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A8255.ZIP contains code that implement a modified 8255 Peripherial Port Controller. The code is written in verilog and project is made for XILINX ISE.
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xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
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备注：使用的是VeriLog HDL语言
软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e .
功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
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rax2 fft implation the fft in
verilog instance and in ise of xilinx
it show how to istance fft core and the port used
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包括三个文档:
1.基于Altera Quartus II 的模块化设计应用
2.基于Xilinx ISE的的模块化设计示例
3.模块化设计方法的设计流程-Consists of three documents: 1. Based on Altera Quartus II modular design applications 2. Xilinx ISE based on the modular design of Example 3. Modular Design for desi
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This a verilog code for SPI Master testbench is also provided
spi_top.v
Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided
spi_top.v
Xilinx ISE or Icarus verilog to compile an
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卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
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FPGACPLD设计工具Xilinx ISE 5.X使用详解》配套光盘-FPGACPLDXilinx ISE 5.0--verilog
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很少有完整介绍ISE环境下FPGA开发的资料，这是在Xilinx ISE开发平台下进行FPGA设计比较好的教程，感觉挺不错的-there is few full descr iption ISE FPGA development environment information, which is in the Xilinx ISE development platform for FPGA design is a good tutorial, I feel pretty good
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熟悉掌握VerilogHDL语言并能用其建立基本 的逻辑部件在Xilinx ISE平台进行输入、编辑、 调试、仿真-Familiar with Verilog HDL language and be able to establish its basic logical components in Xilinx ISE platform for input, editing, debugging, simulation
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文件详细讲述了使用XILINX产FPGA在ISE平台开发的方法，介绍了Modelsim，chipscope,textbench等仿真方法，并含大量实例以及源代码(File details on the use of XILINX produced FPGA in the ISE platform development methods, introduced the Modelsim, chipscope, textbench and other simulation methods, and
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Xilinx ISE开发平台实现4位的led灯循环点亮源代码，测试文件及约束(4 bit LED lamp cycle lighting)
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《无线通信FPGA设计》以Xilinx公司的FPGA开发平台为基础，综合FPGA和无线通信技术两个方向，通过大量的FPGA开发实例，较为详尽地描述了无线通信中常用模块的原理和实现流程，包括数字信号处理基础、数字滤波器、多速率信号处理、数字调制与解调、信道编码、系统同步、自适应滤波算法、最佳接收机，以及WCDMA系统的关键技术。《无线通信FPGA设计》概念明确、思路清晰，追求全面、系统、实用，使读者能够在较短的时间内具备无线通信领域的FPGA开发能力。(The design of wireless
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