搜索资源列表
axi_ad9361_tx_channel
- 采用硬件描述语言verilog进行AD9361芯片实现的代码-AD9361 using hardware descr iption languages Verilog code that chip
hdl-master
- AD9361的ip核，已经调试通过，在vivado上可以运行通。AD9361是一个双通道的便捷收发器，通常用于3G/4G基站。-AD9361' s ip nuclear, debugging has been passed on vivado can run through. AD9361 is a dual-channel transceiver convenient, usually used in 3G/4G base stations.
CFO
- zedboard/AD9361平台进行无线收发，在接收端进行频偏估计和补偿的Verilog参考代码。-zedboard/AD9361 platform for wireless transceiver, the receiver frequency offset estimation and compensation, you can refer to the Verilog code.
hdl-master
- ADI ad9361 vivado 下源代码-ADI ad9361 vivado source code
hdl-2014_r2.tar
- AD9361 IP 核，Linux版本，Vivado2014.2(AD9361 IP core, used on Linux, Vivado2014.2.)
hdl-2014_r2
- AD9361 IP核，Windows版本，Vivado2014.2(AD9361 IP core, used on Windows, Vivado2014.2)
hdl-2015_r2.tar
- AD9361 IP核，Linux版本，Vivado2015.2(AD9361 IP core, used on Linux, Vivado2015.2)
hdl-2015_r2
- AD9361 IP核，Windows版本，Vivado2015.2(AD9361 IP core, used on Windows, Vivado2015.2)
hdl-2016_r2.tar
- AD9361 IP核，Linux版本，Vivado2016.2(AD9361 IP core, used on Linux, Vivado2015.2)
hdl-2016_r2
- AD9361 IP核，Windows版本，Vivado2016.2(AD9361 IP core, used on Windows, Vivado2016.2)
SPI_UART
- SPI读写AD9361，通过串口回读关键寄存器读写是否正确。(SPI reads and writes AD9361, reads and writes the key registers correctly through the serial port.)
AD9361
- AD9361资料文档及其寄存器配置参数文档(Ad9361 data and configuration parameter document)