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- 使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide.
razzle
- 使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。和上一个文件razzle差不多，但是产生的效果不一样。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide. And on a razzle almost document,
译码器
- 通过对用硬件描述语言VHDL表示的某个专用部件（如中断控制器、差错控制码编码/译码器，此为译码器）的代码分析，构建它的逻辑结构，加深对相关部件设计技术的理解。 试验平台：MaxPlusII -through the use of VHDL hardware descr iption language said a special components (such as interrupt controllers, error control coding / decoding devic
4x4的数据选择器
- 用vhdl的4x4的数据选择器，在maxplusII下编译、仿真通过。是构成大型数字电路的重要部件。适合vhdl初学者分析学习。-4x4 with the VHDL data selectors, under the maxplusII compiler, simulation through. Yes constitute large-scale digital circuits important components. VHDL Analysis for beginners to lear
lg
- 基于fpga的逻辑分析仪可显示八路波形，实时分析八路波形 -they simply based on the logic analyzer can show that the Eighth Route Army waveform, real-time waveform analysis of the Eighth Route Army
8250
- 用VHDL编写的8250，内附波形分析，设计思路，以及具体的程序代码-prepared using VHDL 8250, enclosing waveform analysis, design ideas, as well as specific code
基于CORDIC算法的FFT
- 采用按时间抽选的基4原位算法和坐标旋转数字式计算机（CORDIC）算法实现了一个FFT实时谱分析系统。-time selected by using the four-situ algorithm and coordinate rotation digital computer (CORDIC) algorithm is one is a real-time FFT spectrum analysis system.
FPGA_SUM99_VHDL_SOURCE
- 基于FPGA的直接数字合成器的设计与分析的代码程序,代码格式为VHDL-FPGA-based Direct Digital Synthesis Design and Analysis of the code procedures for VHDL code format
一篇用VHDL实现快速傅立叶变换的论文
- 一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供-VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat
add_sub_lab2
- 实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus / subtraction device, and the use of logic diagram VHDl descr iption, including analysis and reporting.
VERILOGBLOCK
- 在blocking 模块中按如下写法，仿真与综合的结果会有什么样的变化？作出仿真 波形，分析综合结果。 -in blocking module by the following wording, simulation and synthesis of the results will be what kind of changes? Make simulation waveform analysis and comprehensive results.
cs555.rar
- 这是一个用VHDL语言写的用状态机控制cs5550进行AD转换的代码，里边包含用逻辑分析仪进行分析的文件。具有很强的可移植性。,This is a work written in VHDL language using state machine control cs5550 for AD conversion code inside that contains the logic analyzer with an analysis of documents. Are highly portab
debussy
- Debussy 是NOVAS Software, Inc(思源科技)发展的HDL Debug & Analysis tool，这套软体主要不是用来跑模拟或看波形，它最强大的功能是：能够在HDL source code、schematic diagram、waveform、state bubble diagram之间，即时做trace，协助工程师debug。 本文主要是介绍Debussy的使用，以及如何在Modelsim环境下生成Debussy所需要的fsdb文件-user guide f
vmm_exam
- vmm 验证方法学的学习实例（源代码），分步骤剖析整个验证设计过程-vmm verification methodology of learning examples (source code), the design process step by step analysis of the entire verification
CPU-heat-sink-and-thermal-analysis-of-structural-d
- CPU散热器结构设计与热分析，对于做机械设计的朋友应该有一定的参考作用！-CPU heat sink and thermal analysis of structural design, mechanical design for a friend so there should be some reference!
analysis
- 很经典的华为时序分析资料，用于电路的时序分析-Huawei is the classic time series analysis data for circuit timing analysis
Analysis-Of-The-Dvb-Common-Scrambling-Algorithm.r
- Analysis of the DVB Common Scrambling Algorithm (DVB-CSA) on FPGA implementation. Performance and Security.
Timing-analysis
- FPGA玩转Altera之时序篇，包括时序分析注意事项-Altera play the FPGA XuPian, including timing analysis the matters needing attention
Timing-Analysis
- 关于VHDL/VERILOG进行EDA设计时序分析时需要注意的一些需要注意的问题及处理策略，保证相当实用，请需要的人参考-VHDL/VERILOG the EDA design timing analysis need to pay attention to some issues that need attention and treatment strategies, guaranteed to be quite practical, please need Reference
ANALYSIS-OF-ALL-GATES
- ANALYSIS OF ALL GATE-ANALYSIS OF ALL GATESS