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state_machine
- pci 总线控制主模式状态机，主要功能是实现批次主模式读写功能-Main Mode pci bus control state machine, the main function is to achieve the main batch mode to read and write functions
ModelSim-gaojishiyong--Camp
- FPGA开发仿真工具modelsim的高级进阶教程，包括如何写脚本文件和后台批处理文件-FPGA Development Advanced simulation tools modelsim tutorial, including how to write a scr ipt file and back-office batch file
batch-26.rar
- IMPLEMENTATION OF SOME VHDL AND VERILOG PROGRAM IN FPGA.,IMPLEMENTATION OF SOME VHDL AND VERILOG PROGRAM IN FPGA.
batch-26
- VHDL CODING FOR BASIC DIGITAL CIRCUITS
modelsimPdebussy-batch-processing
- 内容包括采用Windows批处理方式高效执行Verilog仿真验证的方法，采用Modelsim+debussy联合仿真，里面包含一个加法器实例，批处理文件，仿真指令等。-Included with Windows batch efficient implementation of Verilog simulation method, using Modelsim+debussy co-simulation, which contains an example of an adder, batch
uart_fifo
- 一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。-This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.