搜索资源列表
my_fifo_vhdl
- XILINX的FPGA实现的双口ram源码，可作为dsp\\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \\ SDRAM and pci bridge, and can be used directly, through practical projects.
opb_wb
- 这是一个连通OPB和Wishbone Bus的Bridge, 能够让OPB与开源的Wishbone Bus连接通信， 从而使用基于Wishbone的许多开源IP Core
AHBtoAPB.rar
- amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc,amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
pci-transmission-interface-design
- pci传输的接口设计的verilog，未用桥接芯片-pci transmission interface design verilog, unused bridge chip
bridge
- FPGA和A/D转换芯片ad7862的IP，可实现4路数据的采样和读取。 用verilog实现的-FPGA and the A/D conversion chip ad7862' s IP, can achieve 4-way data sampling and reading. Achieved with verilog
Key
- 具有桥式结构的传感器很多，如利用应变原理、磁电阻原理和其他变电阻原理的传感器，可以实现对压力、位移、加速度、磁场等物理量的测试。这种结构的差分输出可以增加灵敏度，也有一定抵消外加干扰的能力。而且有的虽不是差分输出，比如电阻分压式的输出，可以认为是“半桥”，我们还可以人为的加上另一半，即加上一对精密电阻和一个电位器组成另一个分压电路，形成差分输出。每次调节电位器使差分输出为0，抵消零磁电压。-Bridge structure with many sensors, such as the use o
ahbapb
- AMBA2.0标准的AHB2APb桥，代码通过验证-AMBA2.0 standard AHB2APb Bridge, through the verification code
pif2wb_latest.tar
- This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a b
apb2ahb
- verilog code for apb to ahb convert
ActelFPGA_HE_ApplicationNote
- 在手持式设备的应用中(包括智能电话、相机和 MP3 播放器)，用户大多考虑低功耗、 小尺寸，整个系统中除了处理器外，往往需要提供多种通信接口与存储器接口，用于实现对 硬盘、SD 卡、CF 卡以及 USB 的通信等，用 FPGA 来实现这些接口将会是一种理想的解决 方案。本方案采用 Actel 低功耗的 IGLOO 系列作为处理器(PXA270 或 ARM)的桥接器件和 设备控制器，不仅能够大大简化处理器设计的复杂度，而且 IGLOO 的超低功耗 (最小 5μ W)以及超小封装
opencore_crt
- 可以在Altera QuartusII下编译的Open Cores PCI桥源代码，是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
pci_bridge
- 基于WISHBONE的pci桥实现，包括功能模块和测试模块-Based on the pci bridge WISHBONE implementation, including functional modules and test modules
xapp737
- xapp737 from xilinx website : SPI-4.2 to Quad SPI-3 Bridge in Virtex-4 FPGAs
xapp525
- xapp525 from xilinx website: SPI-4.2 to Quad SPI-3 Bridge
PCIBridge
- pci bridge的verilog实现。-the verilog implemetion of PCI Bridge
design-of-ahptoapb-bridge
- design of ahb2apb bridge using xilinx ISE
ahb2apb
- Verilog实现的AHB2APB bridge代码-Verilog code to achieve the AHB2APB bridge
TIs-HDMIDVI-to-LVDS-Bridge-solutions
- This a brief introduction of TI s HDMI/DVI to LVDS Bridge solutions and an component selection guide. It is good reference for mobilephone or tablet PC system developers who need to develop LCD interface. This document provides an overview of H
H bridge CPLD driver
- Verilog H bridge driver with a Enable control