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ltc1196.rar
- TLC1196串行AD控制模块，可以实现对电压的信号采集，并以串行的方式传送到FPGA中,TLC1196 Serial AD control module can be achieved on the voltage of the signal acquisition, and serial transmission of the FPGA
SR_Latch
- RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit i
SystemVerilogImplicitPorts
- The Accellera SystemVerilog language[3] includes two new features designed to remove much of the tedium and verbosity related to building top-level ASIC and FPGA designs from instantiated sub-blocks. These enhancements permit one of two forms of
hw1
- Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y +
cookbook
- VHDL Cookbook including many useful building blocks.
angel_php
- Describe: VHDL Cookbook including many useful building blocks. Develop tools: VHDL | File size:4374KB | Downloads: 0 [TCP/IP Stack] back4.zip <ding_xinyi> upload at 2011-9-17 4:40:30 Describe: UDP java reference reliable transmission,
ALU-and-Register-File
- ALU&Register Files(RF)之實現和其資料路徑的組合，包含了(1)ALU(2)Register File (RF)(3)Serial-in parallel-out register file(4)ALU + RF datapath-To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.