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9.16 fifoasi
- 主要完成数字电视前端信号处理和缓冲作用的verilog源代码,可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
uart_verilog
- 包含UART口的VERILOG源程序,该程序在FPGA上验证通过,可作为芯片设计,或FPGA设计的一个完整IP核,硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
fpga1394
- 这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.-This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.
uP
- 这是8位微处理器的Verilog源代码,可以欠在Flex10k10里面-This is the 8-bit microprocessor Verilog source code, can they owed in Flex10k10
two_d_dct_serial
- altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码,语言是:verilog 性能不错,不过资源消耗有点大,可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be us
risc_cpu
- 这是一个Verilog HDL编写的RISC cpu的程序,该程序共10个子程序,实现了简单的RISC cpu,可供初学者参考,学习硬件描述语言,及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this e
数据结构c描述习题集答案
- 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能,可以进行自增和自减计数,其计数周期为2^N(N为二进制位数)。 二、设计原理 输入/输出说明: d:异步置数数据输入; q:当前计数器数据输出; clock:时钟脉冲; count_en:计数器计数使能控制(1:计数/0:停止计数); updown:计数器进行自加/自减运算控制(1:自加/0:自减); load_d-a counter a reduction, design requirem
system 完成远程通信的整体任务
- Verilog,QuartusII可正确运行,可下载到FPGA上,完成远程通信的整体任务,PC发数据,键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机,需异步串口调试软件-Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and op
mutl16 实现16位移位乘法和除法
- 实现16位移位,可以实现乘法和除法。满足设计要求,实现代码简短,用verilog完成方便,容易操作。-Achieve 16-bit shift, multiplication and division can be achieved. Meet the design requirements to achieve a short code, complete with verilog convenient, easy to operate.
qiangdaqi.rar
- 用verilog编写的抢答器,当主持人宣布“开始比赛”,系统初始化,选手进入“抢答状态”。当某一选手首先按下抢答开关时,相应的指示灯亮,此时抢答器不再接受其他输入信号。电路具有累计分控制(分别用4个4位选手的积分——十六进制数),由主持人控制“加分”。“加分”加分完毕,开始下一轮抢答。电路还可以设有回答问题时间控制。 ,Answer using Verilog prepared, and when the host announced the " start game" , t
dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程,可实现2k8的双口ram,实现数据存储,缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
I2S
- 用verilog实现的 I2S 源码,可以直接通过Quartus运行-I2S implementation by verilog source code can be run directly through the Quartus ~ ~
VGA_FPGA
- 我用FPGA verilog语言写的VGA显示程序,是我做的一个课程设计,在显示器上显示我的学号20082831.当然也可以改的,里面有三个文件,一个是头文件。-FPGA verilog language written with VGA display program, I do a course design, displayed on the monitor my student number 20082831. Of course, can be changed, there are t
cpu-kongzhi
- 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器,使其能够支持基本的指令。 2. 用Verilog HDL实现单时钟CPU控制器,在ISE上进行波形仿真,并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-
FPGA-usb-control
- USB 68013 通用固件 和配套上位机程序以及下位机FPGA程序verilog 可实现USB高速通信-USB 68013 generic PC firmware and supporting procedures and lower computer USB FPGA program can achieve high-speed communications
verilog1
- 用verilog语言编写的6分频分频计数器。分频后用来控制蜂鸣器响,也可以修改代码做成更高分频的计数器。压缩包内也包含此分频器的modelsim仿真文件-Verilog language with 6 frequency divider counter. Frequency and used to control the buzzer sound, you can modify the code to make a higher frequency counter. Compressed pac
EEPROM_RD_WR.rar
- 本程序包含:EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块(eeprom_wr.v)、信号产生模块(signal.v)和顶层模块(top.v) ,这样可以有一个完整的EEPROM的控制模块和测试文件,本文件通过测试。,This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (e
dianti.rar
- 基于verilog的智能电梯代码,能实现6层电梯的运行,Verilog-based intelligent elevator code, can achieve 6-storey elevator running
VHDL语言实现的arm内核
- 5个ram核,arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核,verilog写的,有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心,结构良好,简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目,国防科技大学牛人ShengYu Shen写的,原来放在opencores上,
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码,可用作IP核使用,已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven