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zhengxian
- verilog的正弦函数信号发生器的设计。可生成不同的正弦函数信号波形。-verilog sine function signal generator design. Can generate a different signal waveform of the sine function.
LMS
- 用verilog编写的lms算法。可实现自适应滤波功能-Lms algorithm written in verilog. Adaptive filtering can be achieved
EXP6
- 基于Verilog 的实现秒表的程序 先要安装Quartus II 6.0 可用看到时序仿真-To achieve a stopwatch program Verilog to install Quartus II 6 can be used to see the timing simulation based on
Sflash_device_mannual
- the serial flash controler use by verilog ,you can run it
fpga-fir
- xlinx fpga 利用verilog语言实现fir滤波器功能，完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
newtwo
- 一个verilog程序，每次按键一下就可以产生一个PWM波。-A verilog program, each button click can generate a PWM wave.
another
- 这是一个用数码管显示的verilog语言描述的数字秒表，且引脚已经分配完毕，基于DE2，可直接下载到板子上使用-This is a digital stopwatch with digital display verilog language described, and the pins have been fully allocated, based DE2, can be directly downloaded to the board
txd
- 用verilog实现的串口发送程序，和之前的发送程序可以一起使用，仿真通过-Verilog achieve serial transmission program, and before sending program can be used in conjunction with simulation through
8051_IP_DOC
- K8051单片机是以由VQM原码（Verilog Quartus Mapping File）表达的，在QuartusII环境下能与VHDL、Verilog等其他硬件描述语言混合编译综合，并在单片FPGA中实现全部硬件系统，并完成软件调试。-K8051 microcontroller in by the the VQM original code (Verilog Quartus Mapping File) expression, can under in QuartusII environmen
No.3bujingdianji
- 用Verilog HDL实现步进电机的控制。能智能控制转速。-Stepper motor control using Verilog HDL. Can the intelligent control speed.
ADCcaiyang
- 用Verilog HDL实现ADC采样。-Stepper motor control using Verilog HDL. Can the intelligent control speed.
RISC-CPU
- 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写 含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
ccd
- 自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴-Of write a tcd1209d of timing-driven code, Verilog language, can learn from
prbs
- verilog 格式的prbs数据。可以用于对发射机和接收机的误码率的测试-verilog format prbs data. Can be used for the testing of the transmitter and receiver BER
ps_transfer
- verilog HDL语言编写的8位并串转换，使用状态机实现可综合-Using verilog HDL language realize parallel-to-serial conversion, using the state machine to achieve ，can comprehense
des
- des的Verilog代码（已编译，可直接使用）-des Verilog code (compiled, and can be used directly)
des3
- 3des的Verilog代码（已编译，可直接使用）-3des Verilog code (compiled, and can be used directly)
1602
- 基于Verilog的液晶初始化程序。本程序可初始化基于ＦＰＧＡ的１６０２模块。-Verilog-based LCD initialization procedure. This procedure can initialize the based FPGA module 1602.
verilogHDL
- 本文主要介绍了Verilog HDL 语言的一些基本知识，目的是使初学者能够迅速掌握HDL 设计方法，初步了解并掌握Verilog HDL语言的基本要素，能够读懂简单的设计代码并能 够进行一些简单设计的Verilog HDL建模。-This paper describes some basic knowledge of the Verilog HDL language, so that beginners can quickly grasp the HDL design methods,
uart_Verilog
- 基于Verilog的RS232串口通信实验，可发送256位数据，并在Altera的EP4CE15F17C8芯片上验证成功。-Verilog-based RS232 serial communication experiment, 256-bit data can be sent on Altera' s EP4CE15F17C8 chip authentication is successful.