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uart_state
- 基于状态机编写的串口通信实验，编程语言是Verilog HDL，可发送八位数据，在Altera的EP4CE15F17C8芯片上验证成功。（与另一个发送256位不同的是这个代码比较突出状态机的使用）。-Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verif
clock
- 用 Verilog HDL 设计一个多功能数字钟，包含以下主要功能： 1） 计时，时间以 24 小时制显示； 2） 校时； 3） 闹钟：设定闹钟时间，可利用 LED 闪烁作为闹钟提示； 4） 跑表：启动、停止； 5） 其他。-Using Verilog HDL design a multi-functional digital clock contains the following main functions: 1) time, the time is displayed
LCD_1602
- verilog lcd1602模块代码，只要往里面输入数据即可显示。-The verilog lcd1602 module code, as long as it is entered, input data can be displayed.
24xiaoshijishuqi
- 用verilog编写的24小时计数器，可以用作电子时钟，简单易懂。-Written in verilog 24 hour counter, which can be used as electronic clock, easy to understand.
cmosmt9m001_model
- 该verilog程序是型号为mt9m001的cmos图像传感器的仿真模型，能够输出频率为30Hz不同分辨率的图像。-This code is the simulation model of mt9m001 cmos sensor,it can output 30Hz and different resolution figure.
canbus
- 此例参照SJA1000CAN通信控制器，通过CAN总线控制器完成CAN总线的通信协议。所传文件为CAN总线的VERILOG代码。-This reference SJA1000CAN communication controller, to complete the communication protocol of CAN bus through the CAN bus controller. The transfer document for the CAN bus VERILOG code.
vga
- 此例程为基于FPGAVGA/LCD显示控制的实例，用Verilog语言实现。代码中有详细注释。并有相应的仿真代码，可以验证其功能完整性。-This routine for the FPGAVGA/LCD display control based on examples, using Verilog language. The code has detailed notes. And a simulation code corresponding, can verify its function
FPGA
- 一些verilog语言程序，可在板子上实现流水灯，计数，按键等功能。-Some verilog language program, can be achieved on the board flowing water light, count, buttons, and other functions.
MDIO
- 网络PHY88E1111的 寄存器 通讯协议的 verilog描述 能实现 lookback 能读出PHY的资料-The register communication protocol Verilog descr iption of the network PHY88E1111 lookback can read the PHY data
signal-generator
- Design of DDS signal generator based on VHDL+FPGA, has been through the adjustable, can be directly used, simulation -DDS signal generator circuit design, Verilog source code, can be directly used, simulation
i2c
- I2C总线协议的verilog 可直接应用 -I2C bus protocol verilog can be applied directly
ADC_TCL5510
- 用verilog编写的源代码 可以对此芯片进行相关操作-Written in verilog source code can be related to the operation of this chip
IIC_EEPROM
- 这是FPGA用Verilog写的IIC协议，可以对存储器进行简单的读取。-This is the FPGA using Verilog IIC protocol, you can perform simple memory read.
verilogvga
- 这是FPGA用Verilog写的VGA显示程序。可以显示一个矩形框和一个小矩形。-This is the FPGA using Verilog VGA display program. You can display a rectangular box and a small rectangle.
project2_2
- 7段译码管，用于显示数字，HDl verilog语言编写，能在DE2上运行-7 segment decoder tube used to display numbers, HDl verilog language, can be run on the DE2
jianyijiafaqi
- 采用MAX+PlusII工具编辑设计的Verilog程序设计的简易加法器。可实现10以内的加法计算-Using MAX+PlusII tools to edit the design of Verilog design of a simple adder. Can be realized within 10 addition calculation
Odd-Frequence-Dividing-Circuit
- 一种奇数分频电路的设计方法，采用verilog HDL描述。修改代码中参数可以进行任意奇数分频，包含了设计文档和源代码。-A design of odd frequence dividing circuit is presented, which is described by verilog HDL。Change the parameter in code, one can get any odd numbers of frequence dividing circuit.
can_exm1_sys
- CAN总线的数据采集，FPGA到USB。verilog hdl语言。-CAN bus data acquisition, FPGA to the USB. verilog hdl language.
alarm
- 利用vhdl和verilog两种方式可以实现的fpga芯片的数字钟，其中包含多个可设计改动的个性化模块。源代码利用quartusii平台写作，可移植性很强。-Using vhdl and verilog fpga can be achieved in two ways-chip digital clock, which includes several design changes personality module. Source code using the platform quartu
I2C-code
- I2C总线协议 Verilog源代码.试过，没有错误！可以直接使用-I2C bus protocol Verilog source code. Tried, no errors! Can be used directly